Skip to content

T
TimEX3
Commit 102cfadf authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
Browse files
Options

VHDL : MIK kicker pulse generator optimization 

 On branch development

	modified:   fpga/TimEX3/top.ucf
	modified:   fpga/sources/clk_sources.vhdl
	modified:   fpga/sources/registers_init.vhdl
	modified:   fpga/sources/src_MIK/MIK_detection.vhdl
	modified:   fpga/sources/src_MIK/MIK_leds.vhdl
	modified:   fpga/sources/src_MIK/MIK_top.vhdl
	modified:   fpga/sources/top.vhdl
parent 2c5f641b
Hide whitespace changes
Inline Side-by-side
Showing with 93 additions and 19 deletions
fpga/TimEX3/top.ucf
View file @ 102cfadf
......@@ -7,7 +7,7 @@
# File : top.ucf
# Revision : x.x.x
# Created : October 29, 2012
# Updated : April 29, 2015
# Updated : April 30, 2015
################################################################################
# Author : Jean-Paul Ricaud
# Organization : Synchrotron Soleil
......@@ -312,6 +312,7 @@ NET "pin_WRn" SLEW = FAST;
NET "pin_CLK60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
NET "s_clk60MHz" CLOCK_DEDICATED_ROUTE = TRUE;
PIN "s_clk120MHz_BUFG.O" CLOCK_DEDICATED_ROUTE = TRUE;
NET "pin_inTTL[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "pin_CLK60MHz" TNM_NET = "pin_CLK60MHz";
......
fpga/sources/clk_sources.vhdl
View file @ 102cfadf
......@@ -7,7 +7,7 @@
-- File : clk_sources.vhd
-- Revision : x.x.x
-- Created : October 30, 2012
-- Updated : March 11, 2013
-- Updated : April 29, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -39,12 +39,16 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity clk_sources is
port (
p_clk60MHz : in std_logic; -- clock 60 MHz
p_clk120MHz : out std_logic; -- clock 120 MHz
p_reset : in std_logic; -- reset input
p_clk1kHz : out std_logic; -- clock 0.1 Hz
p_clk500mHz : out std_logic -- clock 0.5 Hz
......@@ -70,12 +74,25 @@ architecture rtl_clk_sources of clk_sources is
signal s_cnt : unsigned (8 downto 0); -- counter
signal s_clk1kHz : std_logic;
signal s_clk500mHz : std_logic;
signal s_clk0 : std_logic;
signal GND_BIT : std_logic;
------------------------------------------------------------------------------
-- Attributes
------------------------------------------------------------------------------
attribute PERIOD : string;
attribute PERIOD of p_clk120MHz : signal is "8 ns";
attribute BUFFER_TYPE : string;
attribute BUFFER_TYPE of p_clk120MHz : signal is "BUFG";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
------------------------------------------------------------------------------
-- 1 kHz clock
process (p_clk60MHz, p_reset)
begin
......@@ -93,6 +110,7 @@ architecture rtl_clk_sources of clk_sources is
end if;
end process;
------------------------------------------------------------------------------
-- 0.5 Hz clock
process (p_reset, s_clk1kHz)
begin
......@@ -120,10 +138,59 @@ architecture rtl_clk_sources of clk_sources is
end if;
end process;
------------------------------------------------------------------------------
-- 120 MHz clock
-- DCM_SP: Digital Clock Manager
-- Spartan-6
-- Xilinx HDL Language Template, version 14.4
GND_BIT <= '0';
DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 16.7, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLK0 => s_clk0, -- 1-bit output: 0 degree clock output
CLK180 => open, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => p_clk120MHz, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => open, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => open, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => s_clk0, -- 1-bit input: Clock feedback input
CLKIN => p_clk60MHz, -- 1-bit input: Clock input
DSSEN => GND_BIT, -- 1-bit input: Unsupported, specify to GND.
PSCLK => GND_BIT, -- 1-bit input: Phase shift clock input
PSEN => GND_BIT, -- 1-bit input: Phase shift enable
PSINCDEC => GND_BIT, -- 1-bit input: Phase shift increment/decrement input
RST => p_reset -- 1-bit input: Active high reset input
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
s_lfsr_lsb <= s_lfsr(15) xnor s_lfsr(14) xnor s_lfsr(12) xnor s_lfsr(3);
p_clk1kHz <= s_clk1kHz;
p_clk1kHz <= s_clk1kHz;
p_clk500mHz <= s_clk500mHz;
end architecture rtl_clk_sources;
fpga/sources/registers_init.vhdl
View file @ 102cfadf
......@@ -9,14 +9,14 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : April 28, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -76,8 +76,8 @@ package registers_init is
-- time between 2 CLK_SR (read only), maximum delay before a missing CLK_SR is signaled
X"00000000", X"000493E0",
-- *** MIK ***
-- pulse width, time between 2 pulses (read only), maximum delay before a missing synchro is signaled
X"000000F0", X"00000000", X"000493E0");
-- time between 2 pulses (read only), maximum delay before a missing synchro is signaled, pulse width
X"00000000", X"000493E0", X"000001E0");
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
......
fpga/sources/src_MIK/MIK_detection.vhdl
View file @ 102cfadf
......@@ -7,7 +7,7 @@
-- File : MIK_detection.vhd
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 29, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -49,6 +49,7 @@ entity MIK_detection is
port (
p_reset : in std_logic; -- global reset
p_clk60MHz : in std_logic; -- 60 MHz clock
p_clk120MHz : in std_logic; -- 120 MHz clock
p_in : in std_logic; -- input
p_pulseWidth : in std_logic_vector (31 downto 0); -- pulse width register
p_csw : in std_logic; -- register chip select
......@@ -84,11 +85,11 @@ architecture rtl_MIK_detection of MIK_detection is
begin
-- Resync input
process (p_reset, p_clk60MHz)
process (p_reset, p_clk120MHz)
begin
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk60MHz)) then
elsif (rising_edge(p_clk120MHz)) then
s_resync <= s_resync (1 downto 0) & p_in;
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
......@@ -108,13 +109,13 @@ architecture rtl_MIK_detection of MIK_detection is
end process;
-- Pulse generation
process (p_reset, s_rstCNT, s_start, p_clk60MHz)
process (p_reset, s_rstCNT, s_start, p_clk120MHz)
begin
if ((p_reset = '1') or (s_rstCNT = '1') or (s_start = '0')) then
s_cntPulseWidth <= X"00000001";
s_end <= '0';
p_out <= '0';
elsif (rising_edge(p_clk60MHz)) then
elsif (rising_edge(p_clk120MHz)) then
-- Counting the hold off time
if (s_cntPulseWidth >= s_cntPulseWidthMax) then
-- Start the gating windows
......@@ -133,7 +134,7 @@ architecture rtl_MIK_detection of MIK_detection is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cntPulseWidthMax <= unsigned (c_wRegister_init(16));
s_cntPulseWidthMax <= unsigned (c_wRegister_init(18));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
......
fpga/sources/src_MIK/MIK_leds.vhdl
View file @ 102cfadf
......@@ -17,7 +17,7 @@
-- File : MIK_leds.vhdl
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 28, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......
fpga/sources/src_MIK/MIK_top.vhdl
View file @ 102cfadf
......@@ -11,7 +11,7 @@
-- File : MIK_top.vhdl
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 29, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -54,6 +54,7 @@ entity MIK_top is
p_MIK_clk1kHz : in std_logic;
p_MIK_clk500mHz : in std_logic;
p_MIK_clk60MHz : in std_logic;
p_MIK_clk120MHz : in std_logic;
p_MIK_pulseWidth : in std_logic_vector (31 downto 0);
p_MIK_missingPulseDelay : in std_logic_vector (31 downto 0);
p_MIK_csw : in std_logic_vector (1 downto 0);
......@@ -87,6 +88,7 @@ architecture rtl_MIK_top of MIK_top is
port map (
p_reset => p_MIK_reset,
p_clk60MHz => p_MIK_clk60MHz,
p_clk120MHz => p_MIK_clk120MHz,
p_in => p_MIK_inTTL, -- TTL in
p_pulseWidth => p_MIK_pulseWidth,
p_csw => p_MIK_csw(0),
......
fpga/sources/top.vhdl
View file @ 102cfadf
......@@ -7,7 +7,7 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : April 29, 2015
-- Updated : April 30, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -168,6 +168,7 @@ architecture rtl_top of top is
signal s_mux_csw : std_logic_vector (15 downto 0);
signal s_mux_csr : std_logic_vector (15 downto 0);
signal s_clk60MHz : std_logic; -- 60 MHz clock
signal s_clk120MHz : std_logic; -- 120 MHz clock
signal s_clk1kHz : std_logic; -- 1 kHz clock
signal s_clk500mhz : std_logic; -- 0.5 Hz clock
signal s_reset : std_logic;
......@@ -225,10 +226,10 @@ architecture rtl_top of top is
-- Attributes
------------------------------------------------------------------------------
attribute PERIOD : string;
attribute PERIOD of s_clk60MHz : signal is "16 ns";
attribute PERIOD of s_clk60MHz : signal is "16 ns";
attribute BUFFER_TYPE : string;
attribute BUFFER_TYPE of s_clk60MHz : signal is "BUFG";
attribute BUFFER_TYPE of s_clk60MHz : signal is "BUFG";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
......@@ -266,7 +267,8 @@ architecture rtl_top of top is
-- Clock generator
clk_gen : entity work.clk_sources (rtl_clk_sources)
port map (
p_clk60MHz => s_clk60mHz, -- clock 60 MHz
p_clk60MHz => s_clk60MHz, -- clock 60 MHz
p_clk120MHz => s_clk120MHz, -- clock 120 MHz
p_reset => s_reset, -- reset in
p_clk1kHz => s_clk1kHz, -- clock 1 KHz
p_clk500mHz => s_clk500mhz -- clock 0.5 Hz
......@@ -596,6 +598,7 @@ architecture rtl_top of top is
p_MIK_clk1kHz => s_clk1kHz,
p_MIK_clk500mHz => s_clk500mhz,
p_MIK_clk60MHz => s_clk60MHz,
p_MIK_clk120MHz => s_clk120MHz,
p_MIK_pulseWidth => s_MIKpulseWidth, -- pulse width
p_MIK_missingPulseDelay => s_MIKmissingPulseDelay, -- maximum delay before a missing synchro
-- pulse is signaled
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment