Added CAD drawing for frequency divider option and binaries files.

On branch master new file: CAD/TimEX3_freqDiv-FP.dwg modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_freqDIV/freqDIV_config.txt

Added CAD drawing for frequency divider option and binaries files.
On branch master new file: CAD/TimEX3_freqDiv-FP.dwg modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_freqDIV/freqDIV_config.txt
618e1548 · Jean-Paul Ricaud · 4563b9be · 618e1548 · 618e1548 · 618e1548
Commit 618e1548 authored Mar 07, 2014 by Jean-Paul Ricaud
Showing with 7132 additions and 7132 deletions

TimEX3_freqDiv-FP.dwg CAD/TimEX3_freqDiv-FP.dwg +0 -0

TimEX3_eeprom.mcs fpga/TimEX3/TimEX3_eeprom.mcs +7126 -7126

freqDIV_config.txt fpga/sources/src_freqDIV/freqDIV_config.txt +6 -6

No files found.
--- a/CAD/TimEX3_freqDiv-FP.dwg
+++ b/CAD/TimEX3_freqDiv-FP.dwg
--- a/fpga/TimEX3/TimEX3_eeprom.mcs
+++ b/fpga/TimEX3/TimEX3_eeprom.mcs
--- a/fpga/sources/src_freqDIV/freqDIV_config.txt
+++ b/fpga/sources/src_freqDIV/freqDIV_config.txt
@@ -36,16 +36,16 @@
 --------------------------------------------------------------------------------

 ===============================================================================
-Configuration : duplication 1 input to 4 outputs
+Configuration : frequency divion for the slicing DG

 SW : 5-4-3-2-1-0
     0-0-0-1-0-0

-IO0 : input  - input signal
-IO1 : output - duplicated signal
-IO2 : output - duplicated signal
-IO3 : output - duplicated signal
-IO4 : output - duplicated signal
+IO0 : input  - input signal CLK_SR
+IO1 : output - CLK_SR / 846 signal
+IO2 : output - CLK_SR / 846 signal
+IO3 : output - CLK_SR / 846 signal
+IO4 : output - CLK_SR / 846 signal

 Green LED on = OK
 Red LED on   = missing trigger on the input