VHDL : corrected a bug in status manager

On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_cPCI/cPCI_statusManager.vhdl

VHDL : corrected a bug in status manager
On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/src_cPCI/cPCI_statusManager.vhdl
8ee6950d · Jean-Paul Ricaud · 1e2013e4 · 8ee6950d · 8ee6950d
Commit 8ee6950d authored Nov 28, 2013 by Jean-Paul Ricaud
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TimEX3_eeprom.mcs fpga/TimEX3/TimEX3_eeprom.mcs +6673 -6673

cPCI_statusManager.vhdl fpga/sources/src_cPCI/cPCI_statusManager.vhdl +3 -3

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--- a/fpga/TimEX3/TimEX3_eeprom.mcs
+++ b/fpga/TimEX3/TimEX3_eeprom.mcs
--- a/fpga/sources/src_cPCI/cPCI_statusManager.vhdl
+++ b/fpga/sources/src_cPCI/cPCI_statusManager.vhdl
@@ -9,7 +9,7 @@
 -- File     : cPCI_statusManager.vhdl
 -- Revision : x.x.x
 -- Created  : December 05, 2012
-- Updated  : November 18, 2013
+-- Updated  : November 28, 2013
 -------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -86,8 +86,8 @@ architecture rtl_cPCI_statusManager of cPCI_statusManager is
    elsif (falling_edge(p_clk60MHz)) then
      case p_cfgSW is
        when "000000" => s_status <= "00000000" & p_inStates(0);
-        when "000001" => s_status <= "000000"   & p_inStates(3 downto 1);
-        when "000010" => s_status <= "00000000" & p_inStates(4);
+        when "000001" => s_status <= "00000"    & p_inStates(4 downto 1);
+        when "000010" => s_status <= "00000000" & p_inStates(5);
        when "000011" => s_status <= "000000"   & p_inStates(8 downto 6);
        when others   => s_status <= "000000000";
      end case;