DWG : added front panel for clock padding function

On branch development new file: CAD/TimEX3_clkpadding-FP.dwg modified: fpga/sources/src_clkpadding/clkpadding_config.txt modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl

DWG : added front panel for clock padding function
On branch development new file: CAD/TimEX3_clkpadding-FP.dwg modified: fpga/sources/src_clkpadding/clkpadding_config.txt modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl
b09c456a · Jean-Paul Ricaud · 4810e869 · b09c456a · b09c456a · b09c456a
Commit b09c456a authored Oct 08, 2014 by Jean-Paul Ricaud
Showing with 5 additions and 5 deletions

TimEX3_clkpadding-FP.dwg CAD/TimEX3_clkpadding-FP.dwg +0 -0

clkpadding_config.txt fpga/sources/src_clkpadding/clkpadding_config.txt +4 -4

clkpadding_top.vhdl fpga/sources/src_clkpadding/clkpadding_top.vhdl +1 -1

No files found.
--- a/CAD/TimEX3_clkpadding-FP.dwg
+++ b/CAD/TimEX3_clkpadding-FP.dwg
--- a/fpga/sources/src_clkpadding/clkpadding_config.txt
+++ b/fpga/sources/src_clkpadding/clkpadding_config.txt
@@ -7,7 +7,7 @@
 -- File     : clkpadding_config.txt
 -- Revision : x.x.x
 -- Created  : September 19, 2014
-- Updated  : September 19, 2014
+-- Updated  : October 06, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -36,19 +36,19 @@
 --------------------------------------------------------------------------------

 ===============================================================================
-Configuration : duplication 1 input to 4 outputs
+Configuration : clock padding

 SW : 5-4-3-2-1-0
     0-0-0-1-0-1

 IO0 : input  - monitored clock signal
-IO1 : output - storage ring clock signal
+IO1 : input  - storage ring clock signal
 IO2 : output - padded clock signal
 IO3 : output - padded clock signal
 IO4 : output - padded clock signal

 Green LED on = OK
-Red LED on   = missing clock on the input
+Red LED on   = padding going on

 R3, R16, R29, R30, R31 => Qty = 1
 R6, R28, R17, R18, R19 => Qty = 0

--- a/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+++ b/fpga/sources/src_clkpadding/clkpadding_top.vhdl
@@ -146,7 +146,7 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
  p_clkPADDING_outTTL(1) <= '0'; -- not used ; is configured as input
  p_clkPADDING_outTTL(2) <= s_clkPadding;
  p_clkPADDING_outTTL(3) <= s_clkPadding;
-  p_clkPADDING_outTTL(4) <= s_clkPadding;
+  p_clkPADDING_outTTL(4) <= p_clkPADDING_clk_mon;

  p_clkPADDING_outPECL(4 downto 0) <= "00000";