VHDL : added test bench for the synchronized inhibition of LINAC synchro

signals ; corrected some bugs On branch development modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl new file: fpga/sources/testbench/linacSYNCLOCK_tb.vhdl

VHDL : added test bench for the synchronized inhibition of LINAC synchro
signals ; corrected some bugs On branch development modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl new file: fpga/sources/testbench/linacSYNCLOCK_tb.vhdl
bb09df8a · Jean-Paul Ricaud · 94502c11 · bb09df8a · bb09df8a · bb09df8a
Commit bb09df8a authored Dec 02, 2014 by Jean-Paul Ricaud
3 changed files
--- a/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
+++ b/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_synchroInterlock.vhdl
@@ -10,7 +10,7 @@
 -- File     : linacSYNCLOCK_synchroInterlock.vhdl
 -- Revision : x.x.x
 -- Created  : November 28, 2014
-- Updated  : December 01, 2014
+-- Updated  : December 02, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -87,14 +87,12 @@ architecture rtl_linacSYNCLOCK_synchroInterlock of linacSYNCLOCK_synchroInterloc
  begin

  -- Monitor the pre-charge event to start the countdown
-  process (s_reset, p_clk60MHz)
+  process (s_reset, p_precharge)
  begin
    if (s_reset = '1') then
      s_start_contdown <= '0';
-    elsif (rising_edge(p_clk60MHz)) then
-      if (p_precharge = '1') then
-        s_start_contdown <= '1';
-      end if;
+    elsif (rising_edge(p_precharge)) then
+      s_start_contdown <= '1';
    end if;
  end process;


--- a/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
+++ b/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
@@ -16,11 +16,13 @@
 --        : start countdown     : t freez : wait next pre-charge
 --        : interlock monitored : freezed : interlock monitored
 --
+--     p_linacSYNCLOCK_inTTL(0) = pre-charge event
+--     p_linacSYNCLOCK_inTTL(1) = interlock signal
 --------------------------------------------------------------------------------
 -- File     : linacSYNCLOCK_top.vhdl
 -- Revision : x.x.x
 -- Created  : November 28, 2014
-- Updated  : December 01, 2014
+-- Updated  : December 02, 2014
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -79,6 +81,7 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------
+  signal s_holdPrecharge : std_logic_vector (2 downto 0);
  signal s_holdInterlock : std_logic_vector (2 downto 0);
  signal s_linacSYNCLOCK_synchro_interlock : std_logic;

@@ -87,13 +90,17 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
  ------------------------------------------------------------------------------
  begin

-  -- Synchronization of the external async interlock signal with the 60MHz clock
+  -- Synchronization of the external async signals with the 60MHz clock
  process (p_linacSYNCLOCK_clk60MHz, p_linacSYNCLOCK_reset)
  begin
    if (p_linacSYNCLOCK_reset = '1') then
+      s_holdPrecharge <= (OTHERS => '0');
      s_holdInterlock <= (OTHERS => '0');
    elsif (rising_edge(p_linacSYNCLOCK_clk60MHz)) then
-      s_holdInterlock(0) <= p_linacSYNCLOCK_inTTL(1);
+      s_holdPrecharge(0) <= p_linacSYNCLOCK_inTTL(0);  -- pre-charge signal
+      s_holdPrecharge(1) <= s_holdPrecharge(0);
+      s_holdPrecharge(2) <= s_holdPrecharge(1);
+      s_holdInterlock(0) <= p_linacSYNCLOCK_inTTL(1);  -- interlock signal
      s_holdInterlock(1) <= s_holdInterlock(0);
      s_holdInterlock(2) <= s_holdInterlock(1);
    end if;
@@ -104,7 +111,7 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
      port map (
        p_reset            => p_linacSYNCLOCK_reset,
        p_clk60MHz         => p_linacSYNCLOCK_clk60MHz,
-        p_precharge        => p_linacSYNCLOCK_inTTL(0),         -- pre-charge event
+        p_precharge        => s_holdPrecharge(2),               -- pre-charge event
        p_interlock        => s_holdInterlock(2),               -- interlock signal
        p_synchroInterlock => s_linacSYNCLOCK_synchro_interlock -- synchronized interlock signal
                                                                -- 0 = inhibited

--- a/fpga/sources/testbench/linacSYNCLOCK_tb.vhdl
+++ b/fpga/sources/testbench/linacSYNCLOCK_tb.vhdl
+--------------------------------------------------------------------------------
+-- Title   : LINAC synchronized interlock test bench
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : LINAC synchronized interlock test bench
+--------------------------------------------------------------------------------
+-- File     : linacSYNCLOCK_td.vhdl
+-- Revision : x.x.x
+-- Created  : Decembre 02, 2014
+-- Updated  : Decembre 02, 2014
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - 2014 Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity linacSYNCLOCK_tb is
+end entity linacSYNCLOCK_tb;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture simu_linacSYNCLOCK_tb of linacSYNCLOCK_tb is
+  ------------------------------------------------------------------------------
+  -- constant
+  ------------------------------------------------------------------------------
+  constant Period_60MHz : TIME := 16.67 ps;
+  constant Period_3mHz  : TIME := 340 us;
+
+  ------------------------------------------------------------------------------
+  -- signal
+  ------------------------------------------------------------------------------
+  signal s_reset      : std_logic;
+  signal s_clk60MHz   : std_logic;
+  signal s_clk3mHz    : std_logic;
+  signal s_state      : std_logic;
+  signal s_clkinTTL   : std_logic_vector (1 downto 0);
+  signal s_clkoutTTL  : std_logic_vector (4 downto 0);
+  signal s_clkoutPECL : std_logic_vector (4 downto 0);
+  signal s_outLED     : std_logic_vector (1 downto 0);
+
+  ------------------------------------------------------------------------------
+  --------------------------------- Main ---------------------------------------
+  ------------------------------------------------------------------------------
+  begin
+
+  DUT : entity work.linacSYNCLOCK_top (rtl_linacSYNCLOCK_top)
+    port map (
+      p_linacSYNCLOCK_inTTL    => s_clkinTTL,
+      p_linacSYNCLOCK_outTTL   => s_clkoutTTL,
+      p_linacSYNCLOCK_outPECL  => s_clkoutPECL,
+      p_linacSYNCLOCK_clk60MHz => s_clk60MHz,
+      p_linacSYNCLOCK_reset    => s_reset,
+      p_linacSYNCLOCK_state    => s_state,
+      p_linacSYNCLOCK_led      => s_outLED
+    );
+
+  -- Clock generator
+  process
+  begin
+    s_clk60MHz <= '0';
+    wait for (Period_60MHz / 2);
+    s_clk60MHz <= '1';
+    wait for (Period_60MHz / 2);
+  end process;
+
+  process
+  begin
+    s_clk3mHz <= '1';
+    wait for (Period_3mHz / 2);
+    s_clk3mHz <= '0';
+    wait for (Period_3mHz / 2);
+  end process;
+
+  process
+  begin
+    -- Reset
+    s_clkinTTL(1) <= '0';
+    s_reset <= '0';
+    wait for (Period_60MHz);
+    s_reset <= '1';
+    wait for (Period_60MHz);
+    s_reset <= '0';
+
+    ---------------------------
+    ---------------------------
+    wait for (19.15 us);
+    s_clkinTTL(1) <= '1';
+    wait for (10 us);
+    s_clkinTTL(1) <= '0';
+    wait for (310.85 us);
+
+    ---------------------------
+    ---------------------------
+    wait for (15 us);
+    s_clkinTTL(1) <= '1';
+    wait for (4.15 us);
+    s_clkinTTL(1) <= '0';
+    wait for (290 us);
+
+
+    ---------------------------
+
+    -- *** END ***
+    wait;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  s_clkinTTL(0) <= s_clk3mHz;
+
+end architecture simu_linacSYNCLOCK_tb;