VHDL : changed pin assignement for the LINAC synchronized inhibition

function On branch development modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl

VHDL : changed pin assignement for the LINAC synchronized inhibition
function On branch development modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt modified: fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
edb232e3 · Jean-Paul Ricaud · aff9f900 · edb232e3 · edb232e3
Commit edb232e3 authored Dec 11, 2014 by Jean-Paul Ricaud
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linacSYNCLOCK_config.txt fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt +1 -1

linacSYNCLOCK_top.vhdl fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl +2 -2

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--- a/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt
+++ b/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_config.txt
@@ -40,7 +40,7 @@ Configuration : synchronization of the interlock of the LINAC synchronization
                signals ; 1 inputs - 4 outputs

 SW : 5-4-3-2-1-0
-     0-0-0-1-1-0
+     0-0-0-1-0-1

 IO0 : input  - interlock signal
 IO1 : input  - precharge event

--- a/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
+++ b/fpga/sources/src_linacSYNCLOCK/linacSYNCLOCK_top.vhdl
@@ -97,10 +97,10 @@ architecture rtl_linacSYNCLOCK_top of linacSYNCLOCK_top is
      s_holdPrecharge <= (OTHERS => '0');
      s_holdInterlock <= (OTHERS => '0');
    elsif (rising_edge(p_linacSYNCLOCK_clk60MHz)) then
-      s_holdPrecharge(0) <= p_linacSYNCLOCK_inTTL(0);  -- pre-charge signal
+      s_holdPrecharge(0) <= p_linacSYNCLOCK_inTTL(1);  -- pre-charge signal
      s_holdPrecharge(1) <= s_holdPrecharge(0);
      s_holdPrecharge(2) <= s_holdPrecharge(1);
-      s_holdInterlock(0) <= p_linacSYNCLOCK_inTTL(1);  -- interlock signal
+      s_holdInterlock(0) <= p_linacSYNCLOCK_inTTL(0);  -- interlock signal
      s_holdInterlock(1) <= s_holdInterlock(0);
      s_holdInterlock(2) <= s_holdInterlock(1);
    end if;