VHDL : added 8 bunch frequency division for laser slicing

synchronization On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/registers_init.vhdl modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl new file: fpga/sources/testbench/freqDiv_clkdiv_tb.vhdl modified: fpga/sources/top.vhdl

VHDL : added 8 bunch frequency division for laser slicing
synchronization On branch development modified: fpga/TimEX3/TimEX3_eeprom.mcs modified: fpga/sources/registers_init.vhdl modified: fpga/sources/src_clkpadding/clkpadding_top.vhdl modified: fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl new file: fpga/sources/testbench/freqDiv_clkdiv_tb.vhdl modified: fpga/sources/top.vhdl
ef3756b5 · Jean-Paul Ricaud · 73240c33 · ef3756b5 · ef3756b5 · ef3756b5
Commit ef3756b5 authored Mar 02, 2015 by Jean-Paul Ricaud
6 changed files
--- a/fpga/TimEX3/TimEX3_eeprom.mcs
+++ b/fpga/TimEX3/TimEX3_eeprom.mcs
--- a/fpga/sources/registers_init.vhdl
+++ b/fpga/sources/registers_init.vhdl
@@ -78,7 +78,7 @@ package registers_init is

  -- Read registers
  constant c_board_id     : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
-  constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000BE"; -- firmware's version
+  constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000C0"; -- firmware's version

 end package registers_init;


--- a/fpga/sources/src_clkpadding/clkpadding_top.vhdl
+++ b/fpga/sources/src_clkpadding/clkpadding_top.vhdl
@@ -94,16 +94,16 @@ architecture rtl_clkPADDING_top of clkPADDING_top is
  process (p_clkPADDING_reset, s_reset, p_clkPADDING_clk_sr)
  begin
   if ((p_clkPADDING_reset = '1') or (s_reset = '1')) then
-      s_cnt1  <= (OTHERS => '0');
-      s_start <= '0';
-    elsif (rising_edge(p_clkPADDING_clk_sr)) then
-      if (s_cnt1 = c_gapDetect) then
-        s_start <= '1';
-        s_cnt1  <= s_cnt1;
-      else
-        s_cnt1  <= s_cnt1 + 1;
-      end if;
-    end if;
+     s_cnt1  <= (OTHERS => '0');
+     s_start <= '0';
+   elsif (rising_edge(p_clkPADDING_clk_sr)) then
+     if (s_cnt1 = c_gapDetect) then
+       s_start <= '1';
+       s_cnt1  <= s_cnt1;
+     else
+       s_cnt1  <= s_cnt1 + 1;
+     end if;
+   end if;
  end process;

  -- Generation of a padding clock if a gap is detected

--- a/fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
+++ b/fpga/sources/src_freqDIV/freqDIV_clkdiv.vhdl
@@ -3,19 +3,20 @@
 -- Project : TimEX3
 --------------------------------------------------------------------------------
 -- Description : frequency division for DG slicing
--               Fout = 1000.7558192399 Hz = CLK_SR / 846 = slicing laser freq
+--               F1 = F2 = 1000.7558192399 Hz = CLK_SR / 846 = 1 kHz
+--               F3 = F4 = 999.42679425 Hz = CLK_8bunch / 6777 = 8 bunch + 1
 --------------------------------------------------------------------------------
 -- File     : freqDIV_clkdiv.vhd
 -- Revision : x.x.x
 -- Created  : February 03, 2014
-- Updated  : February 03, 2014
+-- Updated  : February 25, 2015
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
 -- Web          : http://www.synchrotron-soleil.fr
 -- Email        : jean-paul.ricaud@synchrotron-soleil.fr
 --------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
+-- Copyright (C) 2012 - 2015 Synchrotron Soleil
 --
 -- This program is free software: you can redistribute it and/or modify
 -- it under the terms of the GNU Lesser General Public License as published by
@@ -40,6 +41,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+Library UNISIM;
+use UNISIM.vcomponents.all;
+
 --------------------------------------------------------------------------------
 --------------------------------- ENTITY ---------------------------------------
 --------------------------------------------------------------------------------
@@ -59,21 +63,29 @@ architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
  ------------------------------------------------------------------------------
  -- constant
  ------------------------------------------------------------------------------
-  constant c_lfsr   : std_logic_vector (8 downto 0) := "111100011";
+  constant c_lfsr               : std_logic_vector (8 downto 0) := "111100011";
+  constant c_8bunch_period_high : unsigned (15 downto 0) := X"0D3C";
+  constant c_8bunch_period      : unsigned (15 downto 0) := X"1A78";

  ------------------------------------------------------------------------------
  -- signal
  ------------------------------------------------------------------------------
-  signal s_lfsr     : std_logic_vector (8 downto 0);
-  signal s_lfsr_lsb : std_logic;
-  signal s_div_423  : std_logic;
-  signal s_div_846  : std_logic;
+  signal s_lfsr      : std_logic_vector (8 downto 0);
+  signal s_lfsr_lsb  : std_logic;
+  signal s_div_423   : std_logic;
+  signal s_1k_SR     : std_logic;
+  signal s_1k_8bunch : std_logic;
+  signal s_clk8bunch : std_logic;
+  signal s_cnt       : unsigned (15 downto 0); -- counter
+
+  signal GND_BIT     : std_logic;

  ------------------------------------------------------------------------------
  --------------------------------- Main ---------------------------------------
  ------------------------------------------------------------------------------
  begin

+  --------------------------- 1 kHz laser clock --------------------------------
  -- s_div_423 = 2001.5116384798 Hz = CLK_SR / 423
  process (p_clkSR, p_reset)
  begin
@@ -91,24 +103,100 @@ architecture rtl_freqDIV_clkdiv of freqDIV_clkdiv is
    end if;
  end process;

-  -- s_div_846 = s_div_423 / 2 = 1000.7558192399 Hz = CLK_SR / 846
+  -- s_1k_SR = s_div_423 / 2 = 1000.7558192399 Hz = CLK_SR / 846
  process (p_reset, s_div_423)
  begin
    if (p_reset = '1') then
-      s_div_846 <= '0';
+      s_1k_SR <= '0';
    elsif (rising_edge(s_div_423)) then
-      s_div_846 <= not s_div_846;
+      s_1k_SR <= not s_1k_SR;
+    end if;
+  end process;
+  ------------------------------------------------------------------------------
+
+  -------------------------- 8 bunch laser clock -------------------------------
+  -- DCM_SP: Digital Clock Manager
+  --         Spartan-6
+  -- Xilinx HDL Language Template, version 14.4
+
+  GND_BIT <= '0';
+
+  DCM_SP_inst : DCM_SP
+  generic map (
+     CLKDV_DIVIDE          => 2.0,                  -- CLKDV divide value
+                                                    -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
+     CLKFX_DIVIDE          => 1,                    -- Divide value on CLKFX outputs - D - (1-32)
+     CLKFX_MULTIPLY        => 8,                    -- Multiply value on CLKFX outputs - M - (2-32)
+     CLKIN_DIVIDE_BY_2     => FALSE,                -- CLKIN divide by two (TRUE/FALSE)
+     CLKIN_PERIOD          => 999.9,               -- Input clock period specified in nS
+     CLKOUT_PHASE_SHIFT    => "NONE",               -- Output phase shift (NONE, FIXED, VARIABLE)
+     CLK_FEEDBACK          => "NONE",               -- Feedback source (NONE, 1X, 2X)
+     DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
+     DFS_FREQUENCY_MODE    => "LOW",                -- Unsupported - Do not change value
+     DLL_FREQUENCY_MODE    => "LOW",                -- Unsupported - Do not change value
+     DSS_MODE              => "NONE",               -- Unsupported - Do not change value
+     DUTY_CYCLE_CORRECTION => TRUE,                 -- Unsupported - Do not change value
+     FACTORY_JF            => X"c080",              -- Unsupported - Do not change value
+     PHASE_SHIFT           => 0,                    -- Amount of fixed phase shift (-255 to 255)
+     STARTUP_WAIT          => FALSE                 -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
+  )
+  port map (
+     CLK0     => open,        -- 1-bit output: 0 degree clock output
+     CLK180   => open,        -- 1-bit output: 180 degree clock output
+     CLK270   => open,        -- 1-bit output: 270 degree clock output
+     CLK2X    => open,        -- 1-bit output: 2X clock frequency clock output
+     CLK2X180 => open,        -- 1-bit output: 2X clock frequency, 180 degree clock output
+     CLK90    => open,        -- 1-bit output: 90 degree clock output
+     CLKDV    => open,        -- 1-bit output: Divided clock output
+     CLKFX    => s_clk8bunch, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
+     CLKFX180 => open,        -- 1-bit output: 180 degree CLKFX output
+     LOCKED   => open,        -- 1-bit output: DCM_SP Lock Output
+     PSDONE   => open,        -- 1-bit output: Phase shift done output
+     STATUS   => open,        -- 8-bit output: DCM_SP status output
+     CLKFB    => GND_BIT,     -- 1-bit input: Clock feedback input
+     CLKIN    => p_clkSR,     -- 1-bit input: Clock input
+     DSSEN    => GND_BIT,     -- 1-bit input: Unsupported, specify to GND.
+     PSCLK    => GND_BIT,     -- 1-bit input: Phase shift clock input
+     PSEN     => GND_BIT,     -- 1-bit input: Phase shift enable
+     PSINCDEC => GND_BIT,     -- 1-bit input: Phase shift increment/decrement input
+     RST      => p_reset      -- 1-bit input: Active high reset input
+  );
+
+  process (p_reset, s_clk8bunch)
+  begin
+    if (p_reset = '1') then
+      s_cnt <= (OTHERS => '0');
+    elsif (rising_edge(s_clk8bunch)) then
+      if (s_cnt = c_8bunch_period) then
+        s_cnt <= (OTHERS => '0');
+      else
+        s_cnt <= s_cnt + 1;
+      end if;
    end if;
  end process;

+  process (p_reset, s_clk8bunch)
+  begin
+    if (p_reset = '1') then
+      s_1k_8bunch <= '1';
+    elsif (rising_edge(s_clk8bunch)) then
+      if (s_cnt < c_8bunch_period_high) then
+        s_1k_8bunch <= '1';
+      else
+        s_1k_8bunch <= '0';
+      end if;
+    end if;
+  end process;
+  ------------------------------------------------------------------------------
+
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  s_lfsr_lsb  <= s_lfsr(8) xnor s_lfsr(4);

-  p_clkOUT(1) <= s_div_846;
-  p_clkOUT(2) <= s_div_846;
-  p_clkOUT(3) <= s_div_846;
-  p_clkOUT(4) <= s_div_846;
+  p_clkOUT(1) <= s_1k_SR;
+  p_clkOUT(2) <= s_1k_SR;
+  p_clkOUT(3) <= s_1k_8bunch;
+  p_clkOUT(4) <= s_1k_8bunch;

  -- Unused signals
  p_clkOUT(0) <= '0'; -- the IO is used as input

--- a/fpga/sources/testbench/freqDiv_clkdiv_tb.vhdl
+++ b/fpga/sources/testbench/freqDiv_clkdiv_tb.vhdl
+--------------------------------------------------------------------------------
+-- Title   : frequency division for DG slicing testbench
+-- Project : TimEX3
+--------------------------------------------------------------------------------
+-- Description : frequency division for DG slicing ; test bench
+--------------------------------------------------------------------------------
+-- File     : freqDiv_clkdiv_tb.vhd
+-- Revision : x.x.x
+-- Created  : October 30, 2012
+-- Updated  : February 26, 2015
+--------------------------------------------------------------------------------
+-- Author       : Jean-Paul Ricaud
+-- Organization : Synchrotron Soleil
+-- Web          : http://www.synchrotron-soleil.fr
+-- Email        : jean-paul.ricaud@synchrotron-soleil.fr
+--------------------------------------------------------------------------------
+-- Copyright (C) 2012 - Synchrotron Soleil
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU Lesser General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU Lesser General Public License for more details.
+--
+-- You should have received a copy of the GNU Lesser General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>
+--------------------------------------------------------------------------------
+--
+--------------------------------------------------------------------------------
+-- Modifications :
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--------------------------------------------------------------------------------
+--------------------------------- ENTITY ---------------------------------------
+--------------------------------------------------------------------------------
+entity freqDiv_clkdiv_tb is
+end entity freqDiv_clkdiv_tb;
+
+--------------------------------------------------------------------------------
+------------------------------- ARCHITECTURE -----------------------------------
+--------------------------------------------------------------------------------
+architecture archi_freqDiv_clkdiv_tb of freqDiv_clkdiv_tb is
+
+  -- constants
+  constant Period_SR  : TIME := 1.181140 us;
+
+  -- signals
+  signal s_clkSR   : std_logic;
+  signal s_rst     : std_logic;
+  signal s_clkOUT  : std_logic_vector (4 downto 0);
+  signal s_outPECL : std_logic_vector (4 downto 0);
+
+  ----------------------------------------------------------------------------
+  ----------------------------------------------------------------------------
+  begin
+
+  -- Frequency divider
+  DUT : entity work.freqDIV_clkdiv (rtl_freqDIV_clkdiv)
+  port map (
+    p_clkSR   => s_clkSR,
+    p_reset   => s_rst,
+    p_clkOUT  => s_clkOUT,
+    p_outPECL => s_outPECL
+  );
+
+  -- Clock generator
+  process
+  begin
+    s_clkSR <= '0';
+    wait for (Period_SR / 2);
+    s_clkSR <= '1';
+    wait for (Period_SR / 2);
+  end process;
+
+  process
+  begin
+    -- Init states
+    s_rst <= '0';
+    wait for 10 ns;
+    s_rst <= '1';
+    wait for 10 ns;
+    s_rst <= '0';
+
+    -- *** END ***
+    wait;
+  end process;
+
+  -----------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+
+end architecture archi_freqDiv_clkdiv_tb;
--- a/fpga/sources/top.vhdl
+++ b/fpga/sources/top.vhdl
@@ -7,7 +7,7 @@
 -- File     : top.vhd
 -- Revision : x.x.x
 -- Created  : October 26, 2012
-- Updated  : December 01, 2014
+-- Updated  : February 26, 2015
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -55,6 +55,8 @@
 --     * Changed the configuration switch of the clock padding from
 --         0-0-0-1-0-1 to 0-0-0-1-1-0
 --     * Added synchronized interlock of the LINAC's synchronization signals
+--   Version 1.9.2 ; February 27, 2015 ; Jean-Paul Ricaud
+--     * Added frequency divider for 8 bunch + 1 period laser clock
 --
 --------------------------------------------------------------------------------