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Commit f379b568 authored by Jean-Paul Ricaud's avatar Jean-Paul Ricaud
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VHDL : work on progress to add the MIK pulse generator 

 On branch development

	modified:   fpga/sources/registers_init.vhdl
	new file:   fpga/sources/src_MIK/MIK_detection.vhdl
	modified:   fpga/sources/src_MIK/MIK_duplication.vhdl
	modified:   fpga/sources/src_MIK/MIK_leds.vhdl
	modified:   fpga/sources/src_MIK/MIK_monitoring.vhdl
	modified:   fpga/sources/src_MIK/MIK_top.vhdl
	modified:   fpga/sources/src_cPCI/cPCI_registerMux.vhdl
	modified:   fpga/sources/src_duplication/dup_top.vhdl
	modified:   fpga/sources/top.vhdl
parent 92df43b2
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fpga/sources/registers_init.vhdl
View file @ f379b568
......@@ -9,7 +9,7 @@
-- File : registers_init.vhdl
-- Revision : x.x.x
-- Created : March 06, 2013
-- Updated : November 28, 2014
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......@@ -74,11 +74,14 @@ package registers_init is
X"00000000", X"000493E0", X"00000000", X"000493E0", X"00000000", X"00000000",
-- *** Frequency divider ***
-- time between 2 CLK_SR (read only), maximum delay before a missing CLK_SR is signaled
X"00000000", X"000493E0");
X"00000000", X"000493E0",
-- *** MIK ***
-- pulse width, time between 2 pulses (read only), maximum delay before a missing synchro is signaled
X"000000F0", X"00000000", X"000493E0");
-- Read registers
constant c_board_id : std_logic_vector (31 downto 0) := X"4AC0FA5C"; -- board ID for TimEX3
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000C0"; -- firmware's version
constant c_firmware_rev : std_logic_vector (31 downto 0) := X"000000C1"; -- firmware's version
end package registers_init;
......
fpga/sources/src_MIK/MIK_detection.vhdl 0 → 100755
View file @ f379b568
--------------------------------------------------------------------------------
-- Title : Detection block
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Signal detection
--------------------------------------------------------------------------------
-- File : MIK_detection.vhd
-- Revision : x.x.x
-- Created : April 28, 2015
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Modifications :
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity MIK_detection is
port (
p_reset : in std_logic; -- global reset
p_clk60MHz : in std_logic; -- 60 MHz clock
p_in : in std_logic; -- input
p_pulseWidth : in std_logic_vector (31 downto 0); -- pulse width register
p_csw : in std_logic; -- register chip select
p_out : out std_logic -- output
);
end MIK_detection;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
-- TTL detection
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture rtl_MIK_detection of MIK_detection is
-- constant
-- signal
signal s_resync : std_logic_vector (2 downto 0);
-- s_risingEdge : std_logic;
-- s_fallingEdge : std_logic;
signal s_cntPulseWidth : unsigned (31 downto 0);
signal s_cntPulseWidthMax : unsigned (31 downto 0);
signal s_rstCNT : std_logic;
signal s_delayed : std_logic_vector (4 downto 1);
attribute keep : string;
attribute keep of s_delayed : signal is "True";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Resync input
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_resync <= "000";
elsif (rising_edge(p_clk60MHz)) then
s_resync <= s_resync (1 downto 0) & p_inTTL(0);
-- s_risingEdge <= s_resync(1) and not s_resync(2);
-- s_fallingEdge <= s_resync(2) and not s_resync(1);
end if;
end process;
-- Start
process (p_reset, s_end, s_resync(0))
begin
if ((p_reset = '1') or (s_end ='1')) then
s_start <= '0';
elsif (rising_edge(s_resync(0))) then
s_start <= '1';
else
s_start <= s_start;
end if;
end process;
-- Pulse generation
process (p_reset, s_rstCNT, s_start, p_clk60MHz)
begin
if ((p_reset = '1') or (s_rstCNT = '1') or (s_start = '0')) then
s_cntPulseWidth <= X"00000001";
s_end <= '0';
p_out <= '0';
elsif (rising_edge(p_clk60MHz)) then
-- Counting the hold off time
if (s_cntPulseWidth >= s_cntPulseWidthMax) then
-- Start the gating windows
s_cntPulseWidth <= s_cntPulseWidth;
s_end <= '1';
p_out <= '0';
else
s_cntPulseWidth <= s_cntGateWidth + 1;
s_end <= '0';
p_out <= '1';
end if;
end if;
-- Latch from the register the pulse width
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cntPulseWidthMax <= unsigned (c_wRegister_init(16));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw(1) = '1') then
s_cntPulseWidthMax <= unsigned (p_pulseWidth);
s_rstCNT <= '1';
else
s_cntPulseWidthMax <= s_cntPulseWidthMax;
s_rstCNT <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
end rtl_MIK_detection;
fpga/sources/src_MIK/MIK_duplication.vhdl
View file @ f379b568
......@@ -4,17 +4,17 @@
--------------------------------------------------------------------------------
-- Description : Signal duplication
--------------------------------------------------------------------------------
-- File : dup_duplication.vhd
-- File : MIK_duplication.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : March 13, 2013
-- Created : April 28, 2015
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -42,68 +42,73 @@ use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity dup_duplication is
entity MIK_duplication is
port (
p_inTTL : in std_logic; -- TTL input
p_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_outPECL : out std_logic_vector (4 downto 0) -- LVPECL outputs
p_in : in std_logic; -- input
p_outTTL : out std_logic_vector (4 downto 0); -- TTL outputs
p_outPECL : out std_logic_vector (4 downto 0) -- LVPECL outputs
);
end dup_duplication;
end MIK_duplication;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
-- TTL duplication
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture rtl_dup_duplicationTTL of dup_duplication is
architecture rtl_MIK_duplication of MIK_duplication is
-- constant
constant c_lenght_delayedOut4 : integer := 8;
constant c_lenght_delayedOut3 : integer := 6;
constant c_lenght_delayedOut2 : integer := 4;
constant c_lenght_delayedOut1 : integer := 2;
-- signal
signal s_delayed : std_logic_vector (4 downto 1);
signal s_delayedOut4 : std_logic_vector (c_lenght_delayedOut4 downto 0);
signal s_delayedOut3 : std_logic_vector (c_lenght_delayedOut3 downto 0);
signal s_delayedOut2 : std_logic_vector (c_lenght_delayedOut2 downto 0);
signal s_delayedOut1 : std_logic_vector (c_lenght_delayedOut1 downto 0);
attribute keep : string;
attribute keep of s_delayed : signal is "True";
attribute keep of s_delayedOUT1 : signal is "True";
attribute keep of s_delayedOUT2 : signal is "True";
attribute keep of s_delayedOUT3 : signal is "True";
attribute keep of s_delayedOUT4 : signal is "True";
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
s_delayed(1) <= not p_inTTL;
s_delayed(2) <= not p_inTTL;
s_delayed(3) <= not p_inTTL;
s_delayed(4) <= not p_inTTL;
s_delayedOut4(0) <= not p_in;
genDelay4 : for i in 1 to (c_lenght_delayedOut4) generate
begin
s_delayedOut4(i) <= not s_delayedOut4(i - 1);
end generate genDelay4;
p_outTTL(4) <= not s_delayedOut4(c_lenght_delayedOut4);
s_delayedOut3(0) <= not p_in;
genDelay3 : for i in 1 to (c_lenght_delayedOut3) generate
begin
s_delayedOut3(i) <= not s_delayedOut3(i - 1);
end generate genDelay3;
p_outTTL(3) <= not s_delayedOut3(c_lenght_delayedOut3);
s_delayedOut2(0) <= not p_in;
genDelay2 : for i in 1 to (c_lenght_delayedOut2) generate
begin
s_delayedOut2(i) <= not s_delayedOut2(i - 1);
end generate genDelay2;
p_outTTL(2) <= not s_delayedOut2(c_lenght_delayedOut2);
p_outTTL(1) <= not s_delayed(1);
p_outTTL(2) <= not s_delayed(2);
p_outTTL(3) <= not s_delayed(3);
p_outTTL(4) <= not s_delayed(4);
s_delayedOut1(0) <= not p_in;
genDelay1 : for i in 1 to (c_lenght_delayedOut1) generate
begin
s_delayedOut1(i) <= not s_delayedOut1(i - 1);
end generate genDelay1;
p_outTTL(1) <= not s_delayedOut1(c_lenght_delayedOut1);
-- Unused signals
p_outTTL(0) <= '0'; -- the IO is used as input
p_outPECL <= "00000";
end rtl_dup_duplicationTTL;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
-- LVPECL duplication
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--architecture rtl_dup_duplicationPECL of dup_duplication is
--
-- ------------------------------------------------------------------------------
-- --------------------------------- Main ---------------------------------------
-- ------------------------------------------------------------------------------
-- begin
--
-- p_outPECL(1) <= p_inTTL;
-- p_outPECL(2) <= p_inTTL;
-- p_outPECL(3) <= p_inTTL;
-- p_outPECL(4) <= p_inTTL;
--
-- -- Unused signals
-- p_outPECL(0) <= '0'; -- the IO is used as input
-- p_outTTL <= "00000";
--
--end rtl_dup_duplicationPECL;
end rtl_MIK_duplication;
fpga/sources/src_MIK/MIK_leds.vhdl
View file @ f379b568
......@@ -14,17 +14,17 @@
-- ======|=====================|=====================|=====================
--
--------------------------------------------------------------------------------
-- File : dup_leds.vhdl
-- File : MIK_leds.vhdl
-- Revision : x.x.x
-- Created : November 07, 2012
-- Updated : February 03, 2013
-- Created : April 28, 2015
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -42,9 +42,7 @@
--
--------------------------------------------------------------------------------
-- Modifications :
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication red LED now reacts on rising edge of the signal instead
-- of level
--
--------------------------------------------------------------------------------
library ieee;
......@@ -57,7 +55,7 @@ use work.registers_init.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity dup_leds is
entity MIK_leds is
port (
p_inTTL : in std_logic; -- input TTL
p_clk1kHz : in std_logic;
......@@ -68,12 +66,12 @@ entity dup_leds is
p_reset : in std_logic;
p_led : out std_logic_vector (1 downto 0)
);
end entity dup_leds;
end entity MIK_leds;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_dup_leds of dup_leds is
architecture rtl_MIK_leds of MIK_leds is
------------------------------------------------------------------------------
-- constant
......@@ -174,7 +172,7 @@ architecture rtl_dup_leds of dup_leds is
process (p_reset, p_clk60MHz)
begin
if (p_reset = '1') then
s_cnt2max <= unsigned (c_wRegister_init(1));
s_cnt2max <= unsigned (c_wRegister_init(17));
s_rstCNT <= '0';
elsif (rising_edge(p_clk60MHz)) then
if (p_csw = '1') then
......@@ -191,4 +189,4 @@ architecture rtl_dup_leds of dup_leds is
------------------------------------------------------------------------------
p_led(1) <= s_greenLedON;
end architecture rtl_dup_leds;
end architecture rtl_MIK_leds;
fpga/sources/src_MIK/MIK_monitoring.vhdl
View file @ f379b568
......@@ -6,17 +6,17 @@
-- A 32 bits conter is used to save the time between two synchroization
-- pulses.
--------------------------------------------------------------------------------
-- File : dup_monitoring.vhdl
-- File : MIK_monitoring.vhdl
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : November 29, 2013
-- Created : April 28, 2015
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2013 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -34,9 +34,7 @@
--
--------------------------------------------------------------------------------
-- Modifications :
-- Version 1.6.0 ; November 29 2013 ; Jean-Paul Ricaud
-- * Duplication monitoring now reacts on rising edge of the signal instead
-- of level
--
--------------------------------------------------------------------------------
library ieee;
......@@ -46,7 +44,7 @@ use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------- ENTITY ---------------------------------------
--------------------------------------------------------------------------------
entity dup_monitoring is
entity MIK_monitoring is
port (
p_inTTL : in std_logic; -- TTL input
p_clk1kHz : in std_logic;
......@@ -54,12 +52,12 @@ entity dup_monitoring is
p_monitor : out std_logic_vector (31 downto 0) -- register with the time
-- value between two pulses
);
end dup_monitoring;
end MIK_monitoring;
--------------------------------------------------------------------------------
------------------------------- ARCHITECTURE -----------------------------------
--------------------------------------------------------------------------------
architecture rtl_dup_monitoring of dup_monitoring is
architecture rtl_MIK_monitoring of MIK_monitoring is
------------------------------------------------------------------------------
-- constant
......@@ -119,4 +117,4 @@ architecture rtl_dup_monitoring of dup_monitoring is
------------------------------------------------------------------------------
p_monitor <= std_logic_vector(s_cnt);
end rtl_dup_monitoring;
end rtl_MIK_monitoring;
fpga/sources/src_MIK/MIK_top.vhdl
View file @ f379b568
......@@ -2,7 +2,7 @@
-- Title : Top - MIK pulse extension function
-- Project : TimEX3
--------------------------------------------------------------------------------
-- Description : Top sheet of the duplicationMIK pulse extension block
-- Description : Top sheet of MIK pulse extension block
-- inTTL(0) is duplicated to outTTL[4 donwto 1]
-- outputs are 4 s width pulses
-- outTTL(0) is not used as the board IO connector is hard configured as
......@@ -54,8 +54,9 @@ entity MIK_top is
p_MIK_clk1kHz : in std_logic;
p_MIK_clk500mHz : in std_logic;
p_MIK_clk60MHz : in std_logic;
p_MIK_pulseWidth : in std_logic_vector (31 downto 0);
p_MIK_missingPulseDelay : in std_logic_vector (31 downto 0);
p_MIK_csw : in std_logic;
p_MIK_csw : in std_logic_vector (1 downto 0);
p_MIK_reset : in std_logic;
p_MIK_pulseMon : out std_logic_vector (31 downto 0); -- pulses monitor
p_MIK_led : out std_logic_vector (1 downto 0)
......@@ -70,39 +71,34 @@ architecture rtl_MIK_top of MIK_top is
------------------------------------------------------------------------------
-- constant
------------------------------------------------------------------------------
constant c_lenght_delayedOut4 : integer := 8;
constant c_lenght_delayedOut3 : integer := 6;
constant c_lenght_delayedOut2 : integer := 4;
constant c_lenght_delayedOut1 : integer := 2;
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_impulse : std_logic; -- detection of impulse
signal s_MIK_outTTL : std_logic_vector (4 downto 0);
signal s_delayedOut4 : std_logic_vector (c_lenght_delayedOut4 downto 0);
signal s_delayedOut3 : std_logic_vector (c_lenght_delayedOut3 downto 0);
signal s_delayedOut2 : std_logic_vector (c_lenght_delayedOut2 downto 0);
signal s_delayedOut1 : std_logic_vector (c_lenght_delayedOut1 downto 0);
attribute keep : string;
attribute keep of s_delayedOUT1 : signal is "True";
attribute keep of s_delayedOUT2 : signal is "True";
attribute keep of s_delayedOUT3 : signal is "True";
attribute keep of s_delayedOUT4 : signal is "True";
signal s_outPulse : std_logic;
------------------------------------------------------------------------------
--------------------------------- Main ---------------------------------------
------------------------------------------------------------------------------
begin
-- Signal duplication block (either TTL or LVPECL)
-- duplication : entity work.MIK_duplication (rtl_MIK_duplicationPECL)
duplication : entity work.MIK_duplication (rtl_MIK_duplicationTTL)
-- Input pulse detection block
pulseDetection : entity work.MIK_detection (rtl_MIK_detection)
port map (
p_reset => p_MIK_reset,
p_clk60MHz => p_MIK_clk60MHz,
p_in => p_MIK_inTTL(0), -- TTL in
p_pulseWidth => p_MIK_pulseWidth,
p_csw => p_MIK_csw(0),
p_out => s_outPulse -- out
);
-- Signal duplication block
duplication : entity work.MIK_duplication (rtl_MIK_duplication)
port map (
p_inTTL => p_MIK_inTTL, -- TTL in
p_outTTL => s_MIK_outTTL, -- TTL out
p_outPECL => p_MIK_outPECL -- LVPECL out
p_in => s_outPulse, -- in
p_outTTL => p_MIK_outTTL, -- TTL out
p_outPECL => p_MIK_outPECL -- LVPECL out ; not used
);
-- Signal monitoring block
......@@ -127,7 +123,7 @@ architecture rtl_MIK_top of MIK_top is
p_clk500mHz => p_MIK_clk500mHz,
p_clk60MHz => p_MIK_clk60MHz,
p_missingPulseDelay => p_MIK_missingPulseDelay,
p_csw => p_MIK_csw,
p_csw => p_MIK_csw(1),
p_reset => p_MIK_reset,
p_led => p_MIK_led
);
......@@ -135,33 +131,4 @@ architecture rtl_MIK_top of MIK_top is
------------------------------------------------------------------------------
------------------------------------------------------------------------------
s_delayedOut4(0) <= not s_MIK_outTTL(4);
genDelay4 : for i in 1 to (c_lenght_delayedOut4) generate
begin
s_delayedOut4(i) <= not s_delayedOut4(i - 1);
end generate genDelay4;
p_MIK_outTTL(4) <= not s_delayedOut4(c_lenght_delayedOut4);
s_delayedOut3(0) <= not s_MIK_outTTL(3);
genDelay3 : for i in 1 to (c_lenght_delayedOut3) generate
begin
s_delayedOut3(i) <= not s_delayedOut3(i - 1);
end generate genDelay3;
p_MIK_outTTL(3) <= not s_delayedOut3(c_lenght_delayedOut3);
s_delayedOut2(0) <= not s_MIK_outTTL(2);
genDelay2 : for i in 1 to (c_lenght_delayedOut2) generate
begin
s_delayedOut2(i) <= not s_delayedOut2(i - 1);
end generate genDelay2;
p_MIK_outTTL(2) <= not s_delayedOut2(c_lenght_delayedOut2);
s_delayedOut1(0) <= not s_MIK_outTTL(1);
genDelay1 : for i in 1 to (c_lenght_delayedOut1) generate
begin
s_delayedOut1(i) <= not s_delayedOut1(i - 1);
end generate genDelay1;
p_MIK_outTTL(1) <= not s_delayedOut1(c_lenght_delayedOut1);
-- p_MIK_outTTL(1) <= s_MIK_outTTL(1);
end architecture rtl_MIK_top;
fpga/sources/src_cPCI/cPCI_registerMux.vhdl
View file @ f379b568
......@@ -5,6 +5,8 @@
-- Description : Register multiplexer
-- SW 5-4-3-2-1-0
-- 1-1-1-1-1-1 : board test
-- 0-0-0-1-1-1 : MIK pulse generator
-- (0-0-0-1-1-0 : NOT REGISTER USED ; clock padding)
-- 0-0-0-1-0-0 : frequency duplication
-- 0-0-0-0-1-1 : LINAC monitoring
-- 0-0-0-0-1-0 : LINAC multipulse
......@@ -14,7 +16,7 @@
-- File : cPCI_registerMux.vhdl
-- Revision : x.x.x
-- Created : November 17, 2013
-- Updated : Ferbuary 03, 2014
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
......
fpga/sources/src_duplication/dup_top.vhdl
View file @ f379b568
......@@ -79,7 +79,6 @@ architecture rtl_dup_top of dup_top is
------------------------------------------------------------------------------
-- signal
------------------------------------------------------------------------------
signal s_impulse : std_logic; -- detection of impulse
signal s_dup_outTTL : std_logic_vector (4 downto 0);
signal s_delayedOut4 : std_logic_vector (c_lenght_delayedOut4 downto 0);
signal s_delayedOut3 : std_logic_vector (c_lenght_delayedOut3 downto 0);
......
fpga/sources/top.vhdl
View file @ f379b568
......@@ -7,14 +7,14 @@
-- File : top.vhd
-- Revision : x.x.x
-- Created : October 26, 2012
-- Updated : February 26, 2015
-- Updated : April 28, 2015
--------------------------------------------------------------------------------
-- Author : Jean-Paul Ricaud
-- Organization : Synchrotron Soleil
-- Web : http://www.synchrotron-soleil.fr
-- Email : jean-paul.ricaud@synchrotron-soleil.fr
--------------------------------------------------------------------------------
-- Copyright (C) 2012 - 2014 Synchrotron Soleil
-- Copyright (C) 2012 - 2015 Synchrotron Soleil
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
......@@ -57,6 +57,8 @@
-- * Added synchronized interlock of the LINAC's synchronization signals
-- Version 1.9.2 ; February 27, 2015 ; Jean-Paul Ricaud
-- * Added frequency divider for 8 bunch + 1 period laser clock
-- Version 1.9.3 ; April 28, 2015 ; Jean-Paul Ricaud
-- * Added MIK Kicker pulse generator
--
--------------------------------------------------------------------------------
......@@ -143,6 +145,10 @@ architecture rtl_top of top is
signal s_freqDivMissingPulseDelay : std_logic_vector (31 downto 0); -- maximum delay before a missing
-- CLK_SR pulse is signaled
signal s_freqDivPulseMon : std_logic_vector (31 downto 0); -- time between 2 CLK_SR pulses
signal s_MIKpulseWidth : std_logic_vector (31 downto 0); -- pulse width
signal s_MIKmissingPulseDelay : std_logic_vector (31 downto 0); -- maximum delay before a missing
-- synchro pulse is signaled
signal s_MIKpulseMon : std_logic_vector (31 downto 0); -- time between 2 pulses
signal s_wRegister : register_array;
signal s_wRegister_init : register_array;
......@@ -155,6 +161,7 @@ architecture rtl_top of top is
signal s_wRegister_foo10 : std_logic_vector (31 downto 0);
signal s_wRegister_foo12 : std_logic_vector (31 downto 0);
signal s_wRegister_foo14 : std_logic_vector (31 downto 0);
signal s_wRegister_foo17 : std_logic_vector (31 downto 0);
signal s_csw : std_logic_vector (20 downto 0); -- chip select of internal write transfert
signal s_csr : std_logic_vector (20 downto 0); -- chip select of internal read transfert
......@@ -204,6 +211,11 @@ architecture rtl_top of top is
signal s_clkPaddingOutPECL : std_logic_vector (4 downto 0);
signal s_clkPaddingLED : std_logic_vector (1 downto 0);
-- MIK pulse generator signals
signal s_MIKOutTTL : std_logic_vector (4 downto 0);
signal s_MIKOutPECL : std_logic_vector (4 downto 0);
signal s_MIKLED : std_logic_vector (1 downto 0);
-- Test signals
signal s_testOutTTL : std_logic_vector (4 downto 0);
signal s_testOutPECL : std_logic_vector (4 downto 0);
......@@ -325,6 +337,10 @@ architecture rtl_top of top is
-- *** Frequency divider ***
-- 20 : 0x18 : time between two CLK_SR pulses (R) [frequency divider mode]
-- 21 : 0x1C : maximum delay before a missing CLK_SR pulse is signaled (R/W) [frequency divider mode]
-- *** MIK pulse generator ***
-- 6 : 0x18 : pulse wodth (R/W) [MIK mode]
-- 6 : 0x1C : time between two synchronization pulses (R) [MIK mode]
-- 7 : 0x20 : maximum delay before a missing synchro pulse is signaled (R/W) [MIK mode]
cPCI_registerMUX : entity work.cPCI_registerMUX (rtl_cPCI_registerMUX)
port map (
-----------------
......@@ -358,6 +374,11 @@ architecture rtl_top of top is
-- (time between 2 CLK_SR pulses)
p_mux_wRegister(15) => s_freqDivMissingPulseDelay, -- maximum delay before a missing synchro
-- pulse is signaled
-- MIK pulse generator
p_mux_wRegister(16) => s_MIKpulseWidth, -- pulse width
p_mux_wRegister(17) => s_wRegister_foo17, -- wRegister_foo17 ; not used read only register
-- (time between 2 pulses)
p_mux_wRegister(18) => s_MIKmissingPulseDelay, -- maximum delay before a missing synchro pulse is signaled
-----------------
-- Read registers
......@@ -383,6 +404,10 @@ architecture rtl_top of top is
-- Frequency divider
p_mux_rRegister(14) => s_freqDivPulseMon, -- time between two CLK_SR pulses
p_mux_rRegister(15) => s_freqDivMissingPulseDelay, -- read back s_freqDivMissingPulseDelay value
-- MIK pulse generation
p_mux_rRegister(16) => s_MIKpulseWidth, -- read back s_MIKpulseWidth value
p_mux_rRegister(17) => s_MIKpulseMon, -- time between two synchronization pulses
p_mux_rRegister(18) => s_MIKmissingPulseDelay, -- read back s_MIKmissingPulseDelay value
-- Write registers
p_wRegister => s_wRegister,
......@@ -418,6 +443,8 @@ architecture rtl_top of top is
-- Status(0) set : time between 2 CLK_SR pulses exceeded the maximum delay [frequency divider mode]
-- *** LINAC synchronized interlock ***
-- Status(0) set : interlock signal is ON [LINAC synchronized interlock mode]
-- *** MIK pulse generator ***
-- Status(0) set : time between 2 synchro pulses exceeded the maximum delay [duplication mode]
cPCI_status: entity work.cPCI_statusManager (rtl_cPCI_statusManager)
port map (
p_inStates(0) => s_dupLED(0), -- time between 2 synchro pulses exceeded the maximum delay
......@@ -431,6 +458,7 @@ architecture rtl_top of top is
p_inStates(8) => s_linacMONLED(0), -- simultaneous SPM / LPM
p_inStates(9) => s_freqDivLED(0), -- time between 2 CLK_SR pulses exceeded the maximum delay
p_inStates(10) => s_linacSYNCLOCKstate, -- interlock state (1 : ON ; 0 : non interlock)
p_inStates(11) => s_MIKLED(0), -- time between 2 synchro pulses exceeded the maximum delay
p_status => s_status,
p_cfgSW => pin_SW, -- configuration switch (duplication, top-up, etc.)
-- Other signals
......@@ -559,6 +587,25 @@ architecture rtl_top of top is
p_clkPADDING_LED => s_clkPaddingLED
);
-- MIK pulse generator block
MIK : entity work.MIK_top (rtl_MIK_top)
port map (
p_MIK_inTTL => pin_inTTL(0),
p_MIK_outTTL => s_MIKOutTTL,
p_MIK_outPECL => s_MIKOutPECL,
p_MIK_clk1kHz => s_clk1kHz,
p_MIK_clk500mHz => s_clk500mhz,
p_MIK_clk60MHz => s_clk60MHz,
p_MIK_pulseWidth => s_MIKpulseWidth, -- pulse width
p_MIK_missingPulseDelay => s_MIKmissingPulseDelay, -- maximum delay before a missing synchro
-- pulse is signaled
p_MIK_csw(0) => s_csw(17),
p_MIK_csw(1) => s_csw(19),
p_MIK_reset => s_reset,
p_MIK_pulseMon => s_MIKpulseMon, -- time between two synchronization pulses
p_MIK_LED => s_MIKLED
);
-- Test
test : entity work.test_top (rtl_test_top)
port map (
......
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