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White Rabbit core collection
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3884a655
Commit
3884a655
authored
Mar 30, 2022
by
Tristan Gingold
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xwrc_platform_xilinx.vhd: remove bufg before plls
(except on spec)
parent
e306a6b0
Pipeline
#4166
failed with stage
Changes
2
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2
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2 changed files
with
17 additions
and
37 deletions
+17
-37
xwrc_board_spec.vhd
board/spec/xwrc_board_spec.vhd
+12
-1
xwrc_platform_xilinx.vhd
platform/xilinx/xwrc_platform_xilinx.vhd
+5
-36
No files found.
board/spec/xwrc_board_spec.vhd
View file @
3884a655
...
...
@@ -313,6 +313,7 @@ architecture struct of xwrc_board_spec is
signal
ext_ref_mul_stopped
:
std_logic
;
signal
ext_ref_rst
:
std_logic
;
signal
clk_125m_pllref_buf_int1
:
std_logic
;
begin
-- architecture struct
-----------------------------------------------------------------------------
...
...
@@ -329,6 +330,16 @@ begin -- architecture struct
I
=>
clk_125m_pllref_p_i
,
IB
=>
clk_125m_pllref_n_i
);
-- The bufg was previously in xwrc_platform_xilinx.
-- However, it is useless except it helps to fit mapping constraints with
-- spartan 45t
-- System PLL input clock buffer
cmp_clk_sys_buf_i
:
BUFG
port
map
(
O
=>
clk_125m_pllref_buf_int1
,
I
=>
clk_125m_pllref_buf
);
cmp_xwrc_platform
:
xwrc_platform_xilinx
generic
map
(
g_fpga_family
=>
"spartan6"
,
...
...
@@ -341,7 +352,7 @@ begin -- architecture struct
areset_n_i
=>
areset_n_i
,
clk_10m_ext_i
=>
clk_10m_ext_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_i
=>
clk_125m_pllref_buf
,
clk_125m_pllref_i
=>
clk_125m_pllref_buf
_int1
,
clk_125m_gtp_p_i
=>
clk_125m_gtp_p_i
,
clk_125m_gtp_n_i
=>
clk_125m_gtp_n_i
,
sfp_txn_o
=>
sfp_txn_o
,
...
...
platform/xilinx/xwrc_platform_xilinx.vhd
View file @
3884a655
...
...
@@ -252,7 +252,6 @@ begin -- architecture rtl
signal
clk_20m_vcxo_buf
:
std_logic
;
signal
clk_pll_aux
:
std_logic_vector
(
3
downto
0
);
signal
clk_125m_pllref_buf_int1
:
std_logic
;
signal
clk_125m_pllref_buf_int2
:
std_logic
;
begin
--gen_spartan6_default_plls
...
...
@@ -302,13 +301,7 @@ begin -- architecture rtl
LOCKED
=>
pll_sys_locked
,
RST
=>
pll_arst
,
CLKFBIN
=>
clk_sys_fb
,
CLKIN
=>
clk_125m_pllref_buf_int1
);
-- System PLL input clock buffer
cmp_clk_sys_buf_i
:
BUFG
port
map
(
O
=>
clk_125m_pllref_buf_int1
,
I
=>
clk_125m_pllref_i
);
CLKIN
=>
clk_125m_pllref_i
);
-- PLL aux clocks buffers
gen_auxclk_bufs
:
for
I
in
0
to
3
generate
...
...
@@ -368,13 +361,7 @@ begin -- architecture rtl
LOCKED
=>
pll_dmtd_locked
,
RST
=>
pll_arst
,
CLKFBIN
=>
clk_dmtd_fb
,
CLKIN
=>
clk_20m_vcxo_buf
);
-- DMTD PLL input clock buffer
cmp_clk_dmtd_buf_i
:
BUFG
port
map
(
O
=>
clk_20m_vcxo_buf
,
I
=>
clk_20m_vcxo_i
);
CLKIN
=>
clk_20m_vcxo_i
);
-- DMTD PLL output clock buffer
cmp_clk_dmtd_buf_o
:
BUFG
...
...
@@ -409,7 +396,7 @@ begin -- architecture rtl
STARTUP_WAIT
=>
FALSE
)
port
map
-- Input clock
(
CLKIN
=>
clk_
ext_buf
,
(
CLKIN
=>
clk_
10m_ext_i
,
CLKFB
=>
clk_ext_fbi
,
-- Output clocks
CLK0
=>
clk_ext_fbo
,
...
...
@@ -428,12 +415,6 @@ begin -- architecture rtl
ext_ref_mul_stopped_o
<=
clk_ext_stat
(
1
);
-- External reference input buffer
cmp_clk_ext_buf_i
:
BUFG
port
map
(
O
=>
clk_ext_buf
,
I
=>
clk_10m_ext_i
);
clk_10m_ext_o
<=
clk_ext_buf
;
-- External reference feedback buffer
...
...
@@ -498,13 +479,7 @@ begin -- architecture rtl
LOCKED
=>
pll_sys_locked
,
RST
=>
pll_arst
,
CLKFBIN
=>
clk_sys_fb
,
CLKIN
=>
clk_125m_pllref_buf
);
-- System PLL input clock buffer
cmp_clk_sys_buf_i
:
BUFG
port
map
(
O
=>
clk_125m_pllref_buf
,
I
=>
clk_125m_pllref_i
);
CLKIN
=>
clk_125m_pllref_i
);
-- System PLL output clock buffer
cmp_clk_sys_buf_o
:
BUFG
...
...
@@ -537,13 +512,7 @@ begin -- architecture rtl
LOCKED
=>
pll_dmtd_locked
,
RST
=>
pll_arst
,
CLKFBIN
=>
clk_dmtd_fb
,
CLKIN
=>
clk_20m_vcxo_buf
);
-- DMTD PLL input clock buffer
cmp_clk_dmtd_buf_i
:
BUFG
port
map
(
O
=>
clk_20m_vcxo_buf
,
I
=>
clk_20m_vcxo_i
);
CLKIN
=>
clk_20m_vcxo_i
);
-- DMTD PLL output clock buffer
cmp_clk_dmtd_buf_o
:
BUFG
...
...
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