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White Rabbit core collection
Commit 50d6bf22 authored by li hongming's avatar li hongming
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support new cute-wr-a7 board

parent fecc11ee
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      .gitignore
      View file @ 50d6bf22
      ......@@ -19,4 +19,5 @@ doc/
      Makefile
      *.xml
      xgui/
      *.orig
      \ No newline at end of file
      *_bd.bmm
      *.orig
      bin/wrpc/wrc_phy16.bram
      View file @ 50d6bf22
      This source diff could not be displayed because it is too large. You can view the blob instead.
      board/common/xwrc_board_common.vhd
      View file @ 50d6bf22
      ......@@ -5,37 +5,39 @@
      -------------------------------------------------------------------------------
      -- File : xwrc_board_common.vhd
      -- Company : CERN (BE-CO-HT)
      -- Created : 2019-06-02
      -- Last update: 2019-06-02
      -- Standard : VHDL'93
      -------------------------------------------------------------------------------
      -- Description: Wrapper for WR PTP core with common features shared between
      -- the various supported boards. These include the core itself, as well as
      -- a selection of fabric interfaces between the core and the application.
      -------------------------------------------------------------------------------
      --
      -- Copyright (c) 2017 CERN
      --
      -- Copyright (c) 2018 CERN
      -------------------------------------------------------------------------------
      -- GNU LESSER GENERAL PUBLIC LICENSE
      --
      -- This source file is free software; you can redistribute it
      -- and/or modify it under the terms of the GNU Lesser General
      -- Public License as published by the Free Software Foundation;
      -- either version 2.1 of the License, or (at your option) any
      -- either version 2.1 of the License,or (at your option) any
      -- later version.
      --
      -- This source is distributed in the hope that it will be
      -- useful, but WITHOUT ANY WARRANTY; without even the implied
      -- useful,but WITHOUT ANY WARRANTY; without even the implied
      -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
      -- PURPOSE. See the GNU Lesser General Public License for more
      -- details.
      --
      -- You should have received a copy of the GNU Lesser General
      -- Public License along with this source; if not, download it
      -- Public License along with this source; if not,download it
      -- from http://www.gnu.org/licenses/lgpl-2.1.html
      --
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      library work;
      use work.gencores_pkg.all;
      ......@@ -45,6 +47,10 @@ use work.wr_fabric_pkg.all;
      use work.endpoint_pkg.all;
      use work.streamers_pkg.all;
      use work.wr_board_pkg.all;
      use work.etherbone_pkg.all;
      library UNISIM;
      use UNISIM.vcomponents.all;
      entity xwrc_board_common is
      generic(
      ......@@ -65,9 +71,15 @@ entity xwrc_board_common is
      g_address_granularity : t_wishbone_address_granularity := BYTE;
      g_aux_sdb : t_sdb_device := c_wrc_periph3_sdb;
      g_aux1_sdb : t_sdb_device := c_wrc_periph3_sdb;
      g_etherbone_sdb : t_sdb_device := c_etherbone_sdb;
      g_softpll_enable_debugger : boolean := FALSE;
      g_vuart_fifo_size : integer := 1024;
      g_pcs_16bit : boolean := FALSE;
      g_pcs_16bit : boolean := TRUE;
      g_ref_clock_rate : integer := 62500000;
      g_sys_clock_rate : integer := 62500000;
      g_ref_clock_hz : integer := 62500000;
      g_sys_clock_hz : integer := 62500000;
      g_ext_clock_rate : integer := 1000000;
      g_diag_id : integer := 0;
      g_diag_ver : integer := 0;
      g_diag_ro_size : integer := 0;
      ......@@ -75,14 +87,9 @@ entity xwrc_board_common is
      g_streamers_op_mode : t_streamers_op_mode := TX_AND_RX;
      g_tx_streamer_params : t_tx_streamer_params := c_tx_streamer_params_defaut;
      g_rx_streamer_params : t_rx_streamer_params := c_rx_streamer_params_defaut;
      -- if WRPC supports only one SFP but we have two connected that are muxed,
      -- mux also the I2C acess to their memory
      g_sfp_i2c_mux_enable : boolean := FALSE;
      g_fabric_iface : t_board_fabric_iface := PLAIN;
      g_num_phys : integer := 1;
      g_num_softpll_inputs : integer := 1;
      g_with_10M_output : boolean := FALSE
      );
      g_fabric_iface : t_board_fabric_iface := ETHERBONE;
      g_with_10M_output : boolean := true;
      g_num_phys : integer := 2);
      port(
      ---------------------------------------------------------------------------
      -- Clocks/resets
      ......@@ -90,10 +97,10 @@ entity xwrc_board_common is
      -- system reference clock (any frequency <= f(clk_ref_i))
      clk_sys_i : in std_logic;
      -- DDMTD offset clock (125.x MHz)
      -- DDMTD offset clock (62.5- MHz)
      clk_dmtd_i : in std_logic;
      -- Timing reference (125 MHz)
      -- Timing reference (125 MHz/62.5MHz)
      clk_ref_i : in std_logic;
      -- Aux clock (i.e. the FMC clock), which can be disciplined by the WR Core
      ......@@ -117,7 +124,6 @@ entity xwrc_board_common is
      ---------------------------------------------------------------------------
      dac_hpll_load_p1_o : out std_logic;
      dac_hpll_data_o : out std_logic_vector(15 downto 0);
      dac_dpll_load_p1_o : out std_logic;
      dac_dpll_data_o : out std_logic_vector(15 downto 0);
      ......@@ -166,7 +172,24 @@ entity xwrc_board_common is
      owr_pwren_o : out std_logic_vector(1 downto 0);
      owr_en_o : out std_logic_vector(1 downto 0);
      owr_i : in std_logic_vector(1 downto 0) := (others => '1');
      -----------------------------------------
      -- PLL chip configuration
      -----------------------------------------
      pll_mosi_o : out std_logic;
      pll_miso_i : in std_logic:='0';
      pll_sck_o : out std_logic;
      pll_cs_n_o : out std_logic;
      pll_sync_n_o : out std_logic;
      pll_reset_n_o : out std_logic;
      -----------------------------------------
      -- EXT IN PLL chip configuration
      -----------------------------------------
      ext_pll_mosi_o : out std_logic;
      ext_pll_miso_i : in std_logic:='0';
      ext_pll_sck_o : out std_logic;
      ext_pll_cs_n_o : out std_logic;
      ext_pll_sync_n_o : out std_logic;
      ext_pll_reset_n_o : out std_logic;
      ---------------------------------------------------------------------------
      --External WB interface
      ---------------------------------------------------------------------------
      ......@@ -177,6 +200,8 @@ entity xwrc_board_common is
      aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
      aux1_master_o : out t_wishbone_master_out;
      aux1_master_i : in t_wishbone_master_in := cc_dummy_master_in;
      eb_cfg_master_o : out t_wishbone_master_out;
      eb_cfg_master_i : in t_wishbone_master_in := cc_dummy_master_in;
      ---------------------------------------------------------------------------
      -- External Fabric I/F (when g_fabric_iface = PLAIN)
      ......@@ -186,6 +211,11 @@ entity xwrc_board_common is
      wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      ---------------------------------------------------------------------------
      -- WR streamers (when g_fabric_iface = STREAMERS)
      ---------------------------------------------------------------------------
      ......@@ -206,7 +236,7 @@ entity xwrc_board_common is
      ---------------------------------------------------------------------------
      wb_eth_master_o : out t_wishbone_master_out;
      wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
      rst_aux_n_o : out std_logic;
      ---------------------------------------------------------------------------
      -- Generic diagnostics interface (access from WRPC via SNMP or uart console
      ---------------------------------------------------------------------------
      ......@@ -251,17 +281,19 @@ entity xwrc_board_common is
      ---------------------------------------------------------------------------
      -- Buttons, LEDs and PPS output
      ---------------------------------------------------------------------------
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- Link ok indication
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      );
      end entity xwrc_board_common;
      ......@@ -272,7 +304,7 @@ architecture struct of xwrc_board_common is
      component eb_ethernet_slave is
      generic(
      g_sdb_address : std_logic_vector(63 downto 0);
      g_timeout_cycles : natural := 6250000; -- 100 ms at 62.5MHz
      g_timeout_cycles : natural := g_sys_clock_rate/10; -- 100 ms at 62.5MHz
      g_mtu : natural := 1500);
      port(
      clk_i : in std_logic;
      ......@@ -296,6 +328,13 @@ architecture struct of xwrc_board_common is
      signal tm_tai : std_logic_vector(39 downto 0);
      signal tm_cycles : std_logic_vector(27 downto 0);
      -- Etherbone WR fabric interface
      signal eb_wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal eb_wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0);
      signal eb_wrf_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal eb_wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0);
      -- WR fabric interface
      signal wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      ......@@ -307,6 +346,10 @@ architecture struct of xwrc_board_common is
      signal aux_master_in : t_wishbone_master_in;
      signal aux_rst_n : std_logic;
      -- Etherbone WB config interface
      signal eb_cfg_master_out : t_wishbone_master_out;
      signal eb_cfg_master_in : t_wishbone_master_in;
      -- Aux diagnostics:
      -- 1) streamers have their own ID not to be used by the users
      -- 2) regardless whether streamers are enabled nor not, application can use diagnostics
      ......@@ -333,17 +376,11 @@ architecture struct of xwrc_board_common is
      -- link state
      signal link_ok : std_logic_vector(g_num_phys-1 downto 0);
      -- ch1 - currently unconnected - not supported at the moment (TODO)
      -- signal sfp1_scl_out : std_logic;
      -- signal sfp1_scl_in : std_logic;
      -- signal sfp1_sda_out : std_logic;
      -- signal sfp1_sda_in : std_logic;
      -- signal sfp1_det_in : std_logic;
      signal pps_valid : std_logic;
      signal pps_csync : std_logic;
      signal ext_ref_pps : std_logic;
      begin -- architecture struct
      -- Check for unsupported fabric interface type
      ......@@ -357,6 +394,14 @@ begin -- architecture struct
      -----------------------------------------------------------------------------
      -- The WR PTP core itself
      -----------------------------------------------------------------------------
      U_Sync_pps_refclk : gc_sync_ffs
      generic map (
      g_sync_edge => "positive")
      port map (
      clk_i => clk_ref_i,
      rst_n_i => '1',
      data_i => pps_ext_i,
      ppulse_o => ext_ref_pps);
      cmp_xwr_core : xwr_core
      generic map (
      ......@@ -377,21 +422,22 @@ begin -- architecture struct
      g_address_granularity => g_address_granularity,
      g_aux_sdb => g_aux_sdb,
      g_aux1_sdb => g_aux1_sdb,
      g_etherbone_sdb => g_etherbone_sdb,
      g_softpll_enable_debugger => g_softpll_enable_debugger,
      g_vuart_fifo_size => g_vuart_fifo_size,
      g_pcs_16bit => g_pcs_16bit,
      g_ref_clock_rate => f_pick_clk_ref_rate(g_pcs_16bit),
      g_ref_clock_hz => f_pick_clk_ref_rate(g_pcs_16bit),
      g_sys_clock_rate => 62500000,
      g_sys_clock_hz => 62500000,
      g_ext_clock_rate => 10000000,
      g_ref_clock_rate => g_ref_clock_rate,
      g_sys_clock_rate => g_sys_clock_rate,
      g_ref_clock_hz => g_ref_clock_hz,
      g_sys_clock_hz => g_sys_clock_hz,
      g_ext_clock_rate => g_ext_clock_rate,
      g_records_for_phy => TRUE,
      g_diag_id => c_diag_id,
      g_diag_ver => c_diag_ver,
      g_diag_ro_size => c_diag_ro_size,
      g_diag_rw_size => c_diag_rw_size,
      g_num_phys => g_num_phys,
      g_num_softpll_inputs => g_num_softpll_inputs,
      g_num_softpll_inputs => 2*g_num_phys,
      g_with_10M_output => g_with_10M_output)
      port map (
      clk_sys_i => clk_sys_i,
      ......@@ -405,29 +451,15 @@ begin -- architecture struct
      clk_ext_rst_o => clk_ext_rst_o,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      todin_term_o => open,
      ext_tai_valid_p_i => '0',
      ext_tai_i => (others => '0'),
      ext_tai_ready_i => '0',
      rst_n_i => rst_n_i,
      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
      dac_hpll_data_o => dac_hpll_data_o,
      dac_dpll_load_p1_o => dac_dpll_load_p1_o,
      dac_dpll_data_o => dac_dpll_data_o,
      phy_ref_clk_i => '0',
      phy_tx_data_o => open,
      phy_tx_k_o => open,
      phy_tx_disparity_i => '0',
      phy_tx_enc_err_i => '0',
      phy_rx_data_i => (others => '0'),
      phy_rx_rbclk_i => '0',
      phy_rx_k_i => (others => '0'),
      phy_rx_enc_err_i => '0',
      phy_rx_bitslide_i => (others => '0'),
      phy_rst_o => open,
      phy_rdy_i => '1',
      phy_loopen_o => open,
      phy_loopen_vec_o => open,
      phy_tx_prbs_sel_o => open,
      phy_sfp_tx_fault_i => '0',
      phy_sfp_los_i => '0',
      phy_sfp_tx_disable_o => open,
      phy8_o => phy8_o,
      phy8_i => phy8_i,
      phy16_o => phy16_o,
      ......@@ -445,25 +477,43 @@ begin -- architecture struct
      sfp_det_i => sfp_det_i,
      btn1_i => btn1_i,
      btn2_i => btn2_i,
      spi_sclk_o => spi_sclk_o,
      spi_ncs_o => spi_ncs_o,
      spi_mosi_o => spi_mosi_o,
      spi_miso_i => spi_miso_i,
      spi_sclk_o => flash_spi_sclk,
      spi_ncs_o => flash_spi_ncs_o,
      spi_mosi_o => flash_spi_mosi_o,
      spi_miso_i => flash_spi_miso_i,
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o,
      owr_pwren_o => owr_pwren_o,
      owr_en_o => owr_en_o,
      owr_i => owr_i,
      ext_pll_mosi_o => ext_pll_mosi_o,
      ext_pll_miso_i => ext_pll_miso_i,
      ext_pll_sck_o => ext_pll_sck_o,
      ext_pll_cs_n_o => ext_pll_cs_n_o,
      ext_pll_sync_n_o => ext_pll_sync_n_o,
      ext_pll_reset_n_o => ext_pll_reset_n_o,
      pll_mosi_o => pll_mosi_o,
      pll_miso_i => pll_miso_i,
      pll_sck_o => pll_sck_o,
      pll_cs_n_o => pll_cs_n_o,
      pll_sync_n_o => pll_sync_n_o,
      pll_reset_n_o => pll_reset_n_o,
      slave_i => wb_slave_i,
      slave_o => wb_slave_o,
      aux_master_o => aux_master_out,
      aux_master_i => aux_master_in,
      aux1_master_o => aux1_master_o,
      aux1_master_i => aux1_master_i,
      eb_cfg_master_o => eb_cfg_master_out,
      eb_cfg_master_i => eb_cfg_master_in,
      wrf_src_o => wrf_src_out,
      wrf_src_i => wrf_src_in,
      wrf_snk_o => wrf_snk_out,
      wrf_snk_i => wrf_snk_in,
      eb_wrf_src_o => eb_wrf_src_out,
      eb_wrf_src_i => eb_wrf_src_in,
      eb_wrf_snk_o => eb_wrf_snk_out,
      eb_wrf_snk_i => eb_wrf_snk_in,
      timestamps_o => timestamps_o,
      timestamps_ack_i => timestamps_ack_i,
      abscal_txts_o => abscal_txts_o,
      ......@@ -483,6 +533,8 @@ begin -- architecture struct
      pps_valid_o => pps_valid,
      pps_p_o => pps_p_o,
      pps_led_o => pps_led_o,
      sync_clk_10m_o_p => sync_clk_10m_o_n,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      rst_aux_n_o => aux_rst_n,
      aux_diag_i => aux_diag_in,
      aux_diag_o => aux_diag_out,
      ......@@ -490,6 +542,7 @@ begin -- architecture struct
      pps_csync_o <= pps_csync;
      pps_valid_o <= pps_valid;
      rst_aux_n_o <= aux_rst_n;
      link_ok_o <= link_ok;
      tm_time_valid_o <= tm_time_valid;
      tm_tai_o <= tm_tai;
      ......@@ -553,19 +606,23 @@ begin -- architecture struct
      port map (
      clk_i => clk_sys_i,
      nrst_i => aux_rst_n,
      src_o => wrf_snk_in(0),
      src_i => wrf_snk_out(0),
      snk_o => wrf_src_in(0),
      snk_i => wrf_src_out(0),
      cfg_slave_o => aux_master_in,
      cfg_slave_i => aux_master_out,
      src_o => eb_wrf_snk_in(0),
      src_i => eb_wrf_snk_out(0),
      snk_o => eb_wrf_src_in(0),
      snk_i => eb_wrf_src_out(0),
      cfg_slave_o => eb_cfg_master_in,
      cfg_slave_i => eb_cfg_master_out,
      master_o => wb_eth_master_o,
      master_i => wb_eth_master_i);
      -- unused output ports
      wrf_src_o <= (others=>c_dummy_snk_in);
      wrf_snk_o <= (others=>c_dummy_src_in);
      wrf_src_o <= wrf_src_out;
      wrf_snk_o <= wrf_snk_out;
      wrf_src_in <= wrf_src_i;
      wrf_snk_in <= wrf_snk_i;
      aux_master_in <= aux_master_i;
      aux_master_o <= aux_master_out;
      wrs_tx_dreq_o <= '0';
      wrs_rx_first_o <= '0';
      wrs_rx_last_o <= '0';
      ......@@ -616,15 +673,24 @@ begin -- architecture struct
      wrs_rx_valid_o <= '0';
      wrs_rx_data_o <= (others => '0');
      wb_eth_master_o <= cc_dummy_master_out;
      eb_wrf_src_o <= eb_wrf_src_out;
      eb_wrf_snk_o <= eb_wrf_snk_out;
      eb_wrf_src_in <= eb_wrf_src_i;
      eb_wrf_snk_in <= eb_wrf_snk_i;
      aux_master_in <= aux_master_i;
      aux_master_o <= aux_master_out;
      eb_cfg_master_in <= eb_cfg_master_i;
      eb_cfg_master_o <= eb_cfg_master_out;
      -- unused inputs to WR PTP core
      aux_diag_in <= aux_diag_i;
      aux_diag_o <= aux_diag_out;
      wb_eth_master_o <= cc_dummy_master_out;
      end generate gen_wr_fabric;
      end architecture struct;
      board/cute/wr_cute_pkg.vhd
      View file @ 50d6bf22
      ......@@ -186,7 +186,7 @@ package wr_cute_pkg is
      addr_first => x"0000000000000000",
      addr_last => x"00000000000000ff",
      product => (
      vendor_id => x"0000000000001103", -- thu
      vendor_id => x"0000000000746875", -- thu
      device_id => x"c0413599",
      version => x"00000001",
      date => x"20160424",
      ......
      board/cute_a7/Manifest.py
      View file @ 50d6bf22
      ......@@ -4,8 +4,7 @@ files = [
      "wr_cute_a7_pkg.vhd",
      "cute_a7_serial_dac_arb.vhd",
      "cute_a7_serial_dac.vhd",
      "xwrc_board_cute_a7.vhd",
      "wr_fdelay_ctrl.vhd"
      "xwrc_board_cute_a7.vhd"
      ]
      modules = {
      ......
      board/cute_a7/wr_cute_a7_pkg.vhd
      View file @ 50d6bf22
      ......@@ -53,7 +53,7 @@ generic(
      g_verbose : boolean := TRUE;
      g_with_external_clock_input : boolean := TRUE;
      g_board_name : string := "cute";
      g_flash_secsz_kb : integer := 256; -- default for N25Q128
      g_flash_secsz_kb : integer := 64; -- default for N25Q128
      g_flash_sdbfs_baddr : integer := 16#760000#; -- default for N25Q128
      g_phys_uart : boolean := TRUE;
      g_virtual_uart : boolean := TRUE;
      ......@@ -104,8 +104,12 @@ port(
      clk_ext_stopped_i : in std_logic := '0';
      clk_ext_rst_o : out std_logic;
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      ---------------------------------------------------------------------------
      --Timing system
      ......@@ -188,6 +192,11 @@ port(
      wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      ---------------------------------------------------------------------------
      -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
      ---------------------------------------------------------------------------
      ......@@ -232,16 +241,18 @@ port(
      ---------------------------------------------------------------------------
      -- Buttons, LEDs and PPS output
      ---------------------------------------------------------------------------
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- Link ok indication
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      );
      ......@@ -249,6 +260,7 @@ end component xwrc_board_cute_a7;
      component wr_pll_ctrl is
      generic (
      g_project_name : string := "normal";
      g_spi_clk_freq : std_logic_vector(31 downto 0) := x"00000004");
      port (
      clk_i : in std_logic;
      ......@@ -268,21 +280,31 @@ port (
      done_o : out std_logic);
      end component wr_pll_ctrl;
      component wr_fdelay_ctrl is
      component xwr_sma_config is
      generic (
      fdelay_ch0 : std_logic_vector(8 downto 0) := (others=>'0');
      fdelay_ch1 : std_logic_vector(8 downto 0) := (others=>'0'));
      g_interface_mode : t_wishbone_interface_mode := PIPELINED;
      g_address_granularity : t_wishbone_address_granularity := WORD
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      clk_serdes_i : in std_logic;
      pps_csync_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_tai_i : in std_logic_vector(39 downto 0);
      sync_data_o_p : out std_logic_vector(1 downto 0);
      sync_data_o_n : out std_logic_vector(1 downto 0);
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end component wr_fdelay_ctrl;
      fdly_en_o : out std_logic;
      fdly_sload_o : out std_logic;
      fdly_sdin_o : out std_logic;
      fdly_sclk_o : out std_logic;
      slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
      slave_o : out t_wishbone_slave_out
      );
      end component;
      constant c_null_sdb : t_sdb_device := (
      abi_class => x"0000", -- undocumented device
      ......@@ -300,5 +322,20 @@ constant c_null_sdb : t_sdb_device := (
      date => x"20201119",
      name => "WR-NULL ")));
      constant c_sma_config_sdb : t_sdb_device := (
      abi_class => x"0000", -- undocumented device
      abi_ver_major => x"01",
      abi_ver_minor => x"01",
      wbd_endian => c_sdb_endian_big,
      wbd_width => x"7", -- 8/16/32-bit port granularity
      sdb_component => (
      addr_first => x"0000000000000000",
      addr_last => x"00000000000000ff",
      product => (
      vendor_id => x"0000000000746875", -- THU
      device_id => x"736d6101",
      version => x"00000001",
      date => x"20210606",
      name => "WR-SMA-Config ")));
      end wr_cute_a7_pkg;
      board/cute_a7/wr_pll_ctrl.vhd
      View file @ 50d6bf22
      ......@@ -8,6 +8,7 @@ use work.wr_pll_ctrl_pkg.all;
      entity wr_pll_ctrl is
      generic (
      g_project_name : string := "NORMAL";
      -- clk_spi = clk/(div+1)/2 --> 6.25MHz sclk for 62.5 input (up to 25MHz)
      g_spi_clk_freq : std_logic_vector(31 downto 0) := x"00000004"
      );
      ......
      board/cute_a7/wr_pll_ctrl_pkg.vhd
      View file @ 50d6bf22
      ......@@ -6,6 +6,7 @@ package wr_pll_ctrl_pkg is
      type t_data_array is array(natural range<>) of std_logic_vector(7 downto 0);
      type t_addr_array is array(natural range<>) of std_logic_vector(15 downto 0);
      -- AD9516 settings for NORMAL
      constant c_spi_addr_array : t_addr_array :=(
      x"0000",x"0001",x"0002",x"0003",x"0004",x"0010",x"0011",x"0012",x"0013",x"0014",x"0015",x"0016",x"0017",x"0018",x"0019",x"001A",
      x"001B",x"001C",x"001D",x"001E",x"001F",x"00A0",x"00A1",x"00A2",x"00A3",x"00A4",x"00A5",x"00A6",x"00A7",x"00A8",x"00A9",x"00AA",
      ......@@ -18,7 +19,7 @@ package wr_pll_ctrl_pkg is
      x"99" ,x"00" ,x"10" ,x"C3" ,x"00" ,x"7C" ,x"05" ,x"00" ,x"0C" ,x"12" ,x"00" ,x"05" ,x"88" ,x"07" ,x"00" ,x"00",
      x"00" ,x"02" ,x"00" ,x"00" ,x"0E" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00",
      x"00" ,x"0A" ,x"0A" ,x"08" ,x"08" ,x"0A" ,x"0A" ,x"42" ,x"42" ,x"42" ,x"42" ,x"00" ,x"08" ,x"00" ,x"00" ,x"80",
      x"00" ,x"00" ,x"80" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"01",
      x"00" ,x"00" ,x"80" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"01",
      x"02" ,x"00" ,x"00" ,x"01"
      );
      ......
      board/cute_a7/xwrc_board_cute_a7.vhd
      View file @ 50d6bf22
      ......@@ -58,14 +58,14 @@ entity xwrc_board_cute_a7 is
      g_verbose : boolean := TRUE;
      g_with_external_clock_input : boolean := TRUE;
      g_board_name : string := "cute";
      g_flash_secsz_kb : integer := 256; -- default for N25Q128
      g_flash_secsz_kb : integer := 64; -- default for N25Q128
      g_flash_sdbfs_baddr : integer := 16#760000#; -- default for N25Q128
      g_phys_uart : boolean := TRUE;
      g_virtual_uart : boolean := TRUE;
      g_aux_clks : integer := 0;
      g_ep_rxbuf_size : integer := 1024;
      g_tx_runt_padding : boolean := TRUE;
      g_dpram_initf : string := "wrc_phy16.bram";
      g_dpram_initf : string := "";
      g_dpram_size : integer := 131072/4;
      g_interface_mode : t_wishbone_interface_mode := PIPELINED;
      g_address_granularity : t_wishbone_address_granularity := BYTE;
      ......@@ -107,15 +107,20 @@ entity xwrc_board_cute_a7 is
      clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
      -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
      clk_ext_i : in std_logic := '0';
      clk_ext_i : in std_logic := '0';
      clk_ext_mul_i : in std_logic := '0';
      clk_ext_mul_locked_i : in std_logic := '1';
      clk_ext_stopped_i : in std_logic := '0';
      clk_ext_rst_o : out std_logic;
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic;
      ext_tai_i : in std_logic_vector(39 downto 0);
      ext_tai_ready_i : in std_logic;
      rst_n_i : in std_logic;
      ---------------------------------------------------------------------------
      ......@@ -129,10 +134,10 @@ entity xwrc_board_cute_a7 is
      ---------------------------------------------------------------------------
      -- PHY I/f
      ---------------------------------------------------------------------------
      phy8_o : out t_phy_8bits_from_wrc_array(g_num_phys-1 downto 0);
      phy8_i : in t_phy_8bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy8_to_wrc);
      phy16_o : out t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      phy16_i : in t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy16_to_wrc);
      phy8_o : out t_phy_8bits_from_wrc_array(g_num_phys-1 downto 0);
      phy8_i : in t_phy_8bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy8_to_wrc);
      phy16_o : out t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      phy16_i : in t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy16_to_wrc);
      ---------------------------------------------------------------------------
      -- I2C EEPROM
      ......@@ -145,12 +150,12 @@ entity xwrc_board_cute_a7 is
      ---------------------------------------------------------------------------
      -- SFP management info
      ---------------------------------------------------------------------------
      sfp_scl_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_scl_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      sfp_sda_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_sda_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      sfp_det_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      -- Flash
      sfp_scl_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_scl_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      sfp_sda_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_sda_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      sfp_det_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      flash_spi_sclk_o : out std_logic;
      flash_spi_ncs_o : out std_logic;
      flash_spi_mosi_o : out std_logic;
      ......@@ -206,6 +211,11 @@ entity xwrc_board_cute_a7 is
      wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      ---------------------------------------------------------------------------
      -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
      ---------------------------------------------------------------------------
      ......@@ -262,10 +272,12 @@ entity xwrc_board_cute_a7 is
      btn2_i : in std_logic := '1';
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p: out std_logic;
      sync_clk_10m_o_n: out std_logic;
      -- Link ok indication
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      );
      ......@@ -282,7 +294,7 @@ architecture struct of xwrc_board_cute_a7 is
      g_mtu : natural := 1500);
      port(
      clk_i : in std_logic;
      nRst_i : in std_logic;
      nrst_i : in std_logic;
      snk_i : in t_wrf_sink_in;
      snk_o : out t_wrf_sink_out;
      src_o : out t_wrf_source_out;
      ......@@ -311,9 +323,9 @@ architecture struct of xwrc_board_cute_a7 is
      -- WR fabric interface
      signal wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      signal wrf_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0);
      signal wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      -- Aux WB interface
      signal aux_master_out : t_wishbone_master_out;
      ......@@ -350,6 +362,10 @@ architecture struct of xwrc_board_cute_a7 is
      -- link state
      signal link_ok : std_logic_vector(g_num_phys-1 downto 0);
      signal pps_valid : std_logic;
      signal pps_csync : std_logic;
      signal pps_unmask : std_logic;
      signal flash_spi_sclk : std_logic;
      begin -- architecture struct
      ......@@ -412,8 +428,12 @@ begin -- architecture struct
      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
      clk_ext_stopped_i => clk_ext_stopped_i,
      clk_ext_rst_o => clk_ext_rst_o,
      pps_ext_i => pps_i,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      rst_n_i => rst_n_i,
      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
      dac_hpll_data_o => dac_hpll_data_o,
      ......@@ -488,16 +508,21 @@ begin -- architecture struct
      tm_time_valid_o => tm_time_valid,
      tm_tai_o => tm_tai,
      tm_cycles_o => tm_cycles,
      pps_csync_o => pps_csync_o,
      pps_p_o => pps_o,
      pps_csync_o => pps_csync,
      pps_valid_o => pps_valid,
      pps_unmask_o => pps_unmask,
      pps_p_o => pps_p_o,
      pps_led_o => pps_led_o,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      sync_clk_10m_o_p => sync_clk_10m_o_p,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      rst_aux_n_o => aux_rst_n,
      aux_diag_i => aux_diag_in,
      aux_diag_o => aux_diag_out,
      link_ok_o => link_ok);
      pps_csync_o <= pps_csync;
      pps_valid_o <= pps_valid;
      pps_unmask_o <= pps_unmask;
      rst_aux_n_o <= aux_rst_n;
      link_ok_o <= link_ok;
      tm_time_valid_o <= tm_time_valid;
      ......@@ -525,10 +550,10 @@ begin -- architecture struct
      cmp_eb_ethernet_slave : eb_ethernet_slave
      generic map (
      g_sdb_address => x"0000000000020e00")
      g_sdb_address => x"0000000000030000")
      port map (
      clk_i => clk_sys_i,
      nRst_i => aux_rst_n,
      nrst_i => aux_rst_n,
      src_o => eb_wrf_snk_in(0),
      src_i => eb_wrf_snk_out(0),
      snk_o => eb_wrf_src_in(0),
      ......@@ -562,6 +587,12 @@ begin -- architecture struct
      wrf_src_in <= wrf_src_i;
      wrf_snk_in <= wrf_snk_i;
      eb_wrf_src_o <= eb_wrf_src_out;
      eb_wrf_snk_o <= eb_wrf_snk_out;
      eb_wrf_src_in <= eb_wrf_src_i;
      eb_wrf_snk_in <= eb_wrf_snk_i;
      aux_master_in <= aux_master_i;
      aux_master_o <= aux_master_out;
      ......
      general-cores @ 8649d40d
      Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
      Subproject commit 8649d40d622bb62ae68580ad57f858920a018c1a
      vme64x-core @ 78cac871
      Subproject commit 78cac8713658de449dcccbce5a5d35131461fc34
      modules/fabric/xwrf_mux.vhd
      View file @ 50d6bf22
      ......@@ -117,7 +117,7 @@ architecture behaviour of xwrf_mux is
      signal dmux_sel : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_status_reg : std_logic_vector(15 downto 0);
      signal dmux_select : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_others : std_logic_vector(g_muxed_ports-1 downto 0);
      -- signal dmux_others : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_sel_zero : std_logic;
      signal dmux_snd_stat : std_logic_vector(g_muxed_ports-1 downto 0);
      signal ep_stall_mask : std_logic;
      ......@@ -206,10 +206,10 @@ begin
      demux <= DMUX_WAIT;
      else
      case demux is
      ---------------------------------------------------------------
      --State DMUX_WAIT: Wait for the WRF cycle to start and then
      -- wait for the STATUS word
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_WAIT: Wait for the WRF cycle to start and then
      -- wait for the STATUS word
      ---------------------------------------------------------------
      when DMUX_WAIT =>
      dmux_select <= (others => '0');
      dmux_snd_stat <= (others => '0');
      ......@@ -221,9 +221,9 @@ begin
      demux <= DMUX_STATUS;
      end if;
      ---------------------------------------------------------------
      --State DMUX_STATUS: Send Status word to appropriate interface
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_STATUS: Send Status word to appropriate interface
      ---------------------------------------------------------------
      when DMUX_STATUS =>
      ep_stall_mask <= '1';
      ......@@ -240,10 +240,10 @@ begin
      demux <= DMUX_PAYLOAD;
      end if;
      ---------------------------------------------------------------
      --State DMUX_PAYLOAD: Just wait here till the end of the
      -- current transfer
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_PAYLOAD: Just wait here till the end of the
      -- current transfer
      ---------------------------------------------------------------
      when DMUX_PAYLOAD =>
      dmux_snd_stat <= (others => '0');
      ep_stall_mask <= '0';
      ......@@ -264,27 +264,26 @@ begin
      -- dmux_others signal says for given interface I if any other interface was
      -- also matched to packet class
      dmux_others(0) <= '0';
      GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
      dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
      end generate;
      -- dmux_others(0) <= '0';
      -- GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
      -- dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
      -- end generate;
      -- Modify the MUX to support multi output by hm
      GEN_DMUX_CONN : for I in 0 to g_muxed_ports-1 generate
      mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1') else
      '0';
      mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.stb when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1') else
      ep_snk_i.stb when(dmux_select(I) = '1') else
      '0';
      mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.adr when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      (others => '0');
      mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.dat when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1') else
      ep_snk_i.adr when(dmux_select(I) = '1') else
      (others => '0');
      mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.sel when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      (others => '1');
      mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1') else
      ep_snk_i.dat;
      mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1') else
      ep_snk_i.sel;
      mux_src_o(I).we <= '1';
      end generate;
      ......
      modules/wr_endpoint/ep_1000basex_pcs.vhd
      View file @ 50d6bf22
      ......@@ -433,8 +433,8 @@ begin -- rtl
      mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
      -- keep PHY reset also when SFP reports LOS (DL)
      serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown
      ;
      -- serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown or serdes_sfp_los_i;
      serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown;
      U_MDIO_WB : ep_pcs_tbi_mdio_wb
      port map (
      ......
      modules/wr_gen_10mhz/xwr_gen_10mhz.vhd
      View file @ 50d6bf22
      ......@@ -59,8 +59,8 @@ port (
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- can be wired to IODelay component in top module for precise 1-PPS
      -- alignment with clk_aux
      ......@@ -310,8 +310,8 @@ begin
      IO_RESET => rst_oserdes
      );
      sync_data_p_o <= sd_out_p(0);
      sync_data_n_o <= sd_out_n(0);
      sync_clk_10m_o_p <= sd_out_p(0);
      sync_clk_10m_o_n <= sd_out_n(0);
      wb_regs_in.pps_ior_tap_cur_i <= ppsdel_tap_i;
      ppsdel_tap_o <= wb_regs_out.pps_ior_tap_set_o;
      ppsdel_tap_wr_o <= wb_regs_out.pps_ior_tap_set_wr_o;
      ......
      modules/wr_pps_gen/pps_gen_regs.h
      View file @ 50d6bf22
      ......@@ -3,7 +3,7 @@
      * File : pps_gen_regs.h
      * Author : auto-generated by wbgen2 from pps_gen_wb.wb
      * Created : Wed Jun 5 16:28:58 2019
      * Created : Sun Mar 5 18:23:51 2023
      * Standard : ANSI C
      THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
      ......@@ -14,7 +14,11 @@
      #ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
      #define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
      #ifdef __KERNEL__
      #include <linux/types.h>
      #else
      #include <inttypes.h>
      #endif
      #if defined( __GNUC__)
      #define PACKED __attribute__ ((packed))
      ......@@ -24,7 +28,7 @@
      #ifndef __WBGEN2_MACROS_DEFINED__
      #define __WBGEN2_MACROS_DEFINED__
      #define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
      #define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
      #define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
      #define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
      #define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
      ......@@ -86,6 +90,19 @@
      /* definitions for field: Enable PPS_IN 50Ohm termination in reg: External sync control register */
      #define PPSG_ESCR_PPS_IN_TERM WBGEN2_GEN_MASK(6, 1)
      /* definitions for field: Enable TOD IN 5OOhm termination in reg: External sync control register */
      #define PPSG_ESCR_TOD_IN_TERM WBGEN2_GEN_MASK(7, 1)
      /* definitions for field: Set UTC counter to External UTC Input in reg: External sync control register */
      #define PPSG_ESCR_EXT_UTC_SYNC WBGEN2_GEN_MASK(8, 1)
      /* definitions for field: External UTC Status in reg: External sync control register */
      #define PPSG_ESCR_EXT_UTC_READY WBGEN2_GEN_MASK(9, 1)
      /* definitions for register: EXT UTC Counter register (least-significant part) */
      /* definitions for register: EXT UTC Counter register (most-significant part) */
      PACKED struct PPSG_WB {
      /* [0x0]: REG Control Register */
      uint32_t CR;
      ......@@ -103,11 +120,10 @@ PACKED struct PPSG_WB {
      uint32_t ADJ_UTCHI;
      /* [0x1c]: REG External sync control register */
      uint32_t ESCR;
      /* [0x20]: REG EXT UTC Counter register (least-significant part) */
      uint32_t EXT_CNTR_UTCLO;
      /* [0x24]: REG EXT UTC Counter register (most-significant part) */
      uint32_t EXT_CNTR_UTCHI;
      };
      #define PPSG_PERIPH_PREFIX "ppsg"
      #define PPSG_PERIPH_NAME "WR Switch PPS generator and RTC"
      #define PPSG_PERIPH_DESC WBGEN2_DESC("Unit generating PPS signals and acting as a UTC real-time clock")
      #endif
      modules/wr_pps_gen/pps_gen_wb.vhd
      View file @ 50d6bf22
      ......@@ -3,7 +3,7 @@
      ---------------------------------------------------------------------------------------
      -- File : pps_gen_wb.vhd
      -- Author : auto-generated by wbgen2 from pps_gen_wb.wb
      -- Created : Wed Jun 5 16:28:58 2019
      -- Created : Sun Mar 5 18:23:51 2023
      -- Standard : VHDL'87
      ---------------------------------------------------------------------------------------
      -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
      ......@@ -18,7 +18,7 @@ entity pps_gen_wb is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(2 downto 0);
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -26,6 +26,8 @@ entity pps_gen_wb is
      wb_stb_i : in std_logic;
      wb_we_i : in std_logic;
      wb_ack_o : out std_logic;
      wb_err_o : out std_logic;
      wb_rty_o : out std_logic;
      wb_stall_o : out std_logic;
      refclk_i : in std_logic;
      -- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Reset counter' in reg: 'Control Register'
      ......@@ -70,7 +72,17 @@ entity pps_gen_wb is
      -- Port for asynchronous (clock: refclk_i) MONOSTABLE field: 'Set nanoseconds counter' in reg: 'External sync control register'
      ppsg_escr_nsec_set_o : out std_logic;
      -- Port for BIT field: 'Enable PPS_IN 50Ohm termination' in reg: 'External sync control register'
      ppsg_escr_pps_in_term_o : out std_logic
      ppsg_escr_pps_in_term_o : out std_logic;
      -- Port for BIT field: 'Enable TOD IN 5OOhm termination' in reg: 'External sync control register'
      ppsg_escr_tod_in_term_o : out std_logic;
      -- Port for BIT field: 'Set UTC counter to External UTC Input' in reg: 'External sync control register'
      ppsg_escr_ext_tai_sync_o : out std_logic;
      -- Port for BIT field: 'External UTC Status' in reg: 'External sync control register'
      ppsg_escr_ext_tai_ready_i : in std_logic;
      -- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'EXT UTC Counter register (least-significant part)'
      ppsg_ext_cntr_utclo_i : in std_logic_vector(31 downto 0);
      -- Port for asynchronous (clock: refclk_i) std_logic_vector field: 'UTC Counter' in reg: 'EXT UTC Counter register (most-significant part)'
      ppsg_ext_cntr_utchi_i : in std_logic_vector(7 downto 0)
      );
      end pps_gen_wb;
      ......@@ -154,11 +166,27 @@ signal ppsg_escr_nsec_set_sync0 : std_logic ;
      signal ppsg_escr_nsec_set_sync1 : std_logic ;
      signal ppsg_escr_nsec_set_sync2 : std_logic ;
      signal ppsg_escr_pps_in_term_int : std_logic ;
      signal ppsg_escr_tod_in_term_int : std_logic ;
      signal ppsg_escr_ext_tai_sync_int : std_logic ;
      signal ppsg_ext_cntr_utclo_int : std_logic_vector(31 downto 0);
      signal ppsg_ext_cntr_utclo_lwb : std_logic ;
      signal ppsg_ext_cntr_utclo_lwb_delay : std_logic ;
      signal ppsg_ext_cntr_utclo_lwb_in_progress : std_logic ;
      signal ppsg_ext_cntr_utclo_lwb_s0 : std_logic ;
      signal ppsg_ext_cntr_utclo_lwb_s1 : std_logic ;
      signal ppsg_ext_cntr_utclo_lwb_s2 : std_logic ;
      signal ppsg_ext_cntr_utchi_int : std_logic_vector(7 downto 0);
      signal ppsg_ext_cntr_utchi_lwb : std_logic ;
      signal ppsg_ext_cntr_utchi_lwb_delay : std_logic ;
      signal ppsg_ext_cntr_utchi_lwb_in_progress : std_logic ;
      signal ppsg_ext_cntr_utchi_lwb_s0 : std_logic ;
      signal ppsg_ext_cntr_utchi_lwb_s1 : std_logic ;
      signal ppsg_ext_cntr_utchi_lwb_s2 : std_logic ;
      signal ack_sreg : std_logic_vector(9 downto 0);
      signal rddata_reg : std_logic_vector(31 downto 0);
      signal wrdata_reg : std_logic_vector(31 downto 0);
      signal bwsel_reg : std_logic_vector(3 downto 0);
      signal rwaddr_reg : std_logic_vector(2 downto 0);
      signal rwaddr_reg : std_logic_vector(3 downto 0);
      signal ack_in_progress : std_logic ;
      signal wr_int : std_logic ;
      signal rd_int : std_logic ;
      ......@@ -166,13 +194,8 @@ signal allones : std_logic_vector(31 downto 0);
      signal allzeros : std_logic_vector(31 downto 0);
      begin
      -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
      -- Some internal signals assignments
      wrdata_reg <= wb_dat_i;
      bwsel_reg <= wb_sel_i;
      rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
      wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
      allones <= (others => '1');
      allzeros <= (others => '0');
      --
      -- Main register bank access process.
      process (clk_sys_i, rst_n_i)
      ......@@ -219,6 +242,14 @@ begin
      ppsg_escr_nsec_set_int <= '0';
      ppsg_escr_nsec_set_int_delay <= '0';
      ppsg_escr_pps_in_term_int <= '0';
      ppsg_escr_tod_in_term_int <= '0';
      ppsg_escr_ext_tai_sync_int <= '0';
      ppsg_ext_cntr_utclo_lwb <= '0';
      ppsg_ext_cntr_utclo_lwb_delay <= '0';
      ppsg_ext_cntr_utclo_lwb_in_progress <= '0';
      ppsg_ext_cntr_utchi_lwb <= '0';
      ppsg_ext_cntr_utchi_lwb_delay <= '0';
      ppsg_ext_cntr_utchi_lwb_in_progress <= '0';
      elsif rising_edge(clk_sys_i) then
      -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ......@@ -273,11 +304,23 @@ begin
      ppsg_escr_sec_set_int_delay <= '0';
      ppsg_escr_nsec_set_int <= ppsg_escr_nsec_set_int_delay;
      ppsg_escr_nsec_set_int_delay <= '0';
      ppsg_ext_cntr_utclo_lwb <= ppsg_ext_cntr_utclo_lwb_delay;
      ppsg_ext_cntr_utclo_lwb_delay <= '0';
      if ((ack_sreg(1) = '1') and (ppsg_ext_cntr_utclo_lwb_in_progress = '1')) then
      rddata_reg(31 downto 0) <= ppsg_ext_cntr_utclo_int;
      ppsg_ext_cntr_utclo_lwb_in_progress <= '0';
      end if;
      ppsg_ext_cntr_utchi_lwb <= ppsg_ext_cntr_utchi_lwb_delay;
      ppsg_ext_cntr_utchi_lwb_delay <= '0';
      if ((ack_sreg(1) = '1') and (ppsg_ext_cntr_utchi_lwb_in_progress = '1')) then
      rddata_reg(7 downto 0) <= ppsg_ext_cntr_utchi_int;
      ppsg_ext_cntr_utchi_lwb_in_progress <= '0';
      end if;
      end if;
      else
      if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
      case rwaddr_reg(2 downto 0) is
      when "000" =>
      case rwaddr_reg(3 downto 0) is
      when "0000" =>
      if (wb_we_i = '1') then
      ppsg_cr_cnt_rst_int <= wrdata_reg(0);
      ppsg_cr_cnt_rst_int_delay <= wrdata_reg(0);
      ......@@ -306,7 +349,7 @@ begin
      rddata_reg(31 downto 4) <= ppsg_cr_pwidth_int;
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "001" =>
      when "0001" =>
      if (wb_we_i = '1') then
      end if;
      if (wb_we_i = '0') then
      ......@@ -320,7 +363,7 @@ begin
      rddata_reg(31) <= 'X';
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "010" =>
      when "0010" =>
      if (wb_we_i = '1') then
      end if;
      if (wb_we_i = '0') then
      ......@@ -330,7 +373,7 @@ begin
      end if;
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "011" =>
      when "0011" =>
      if (wb_we_i = '1') then
      end if;
      if (wb_we_i = '0') then
      ......@@ -364,7 +407,7 @@ begin
      rddata_reg(31) <= 'X';
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "100" =>
      when "0100" =>
      if (wb_we_i = '1') then
      ppsg_adj_nsec_wr_o <= '1';
      end if;
      ......@@ -402,7 +445,7 @@ begin
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "101" =>
      when "0101" =>
      if (wb_we_i = '1') then
      ppsg_adj_utclo_wr_o <= '1';
      end if;
      ......@@ -440,7 +483,7 @@ begin
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "110" =>
      when "0110" =>
      if (wb_we_i = '1') then
      ppsg_adj_utchi_wr_o <= '1';
      end if;
      ......@@ -478,7 +521,7 @@ begin
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "111" =>
      when "0111" =>
      if (wb_we_i = '1') then
      ppsg_escr_sync_int_write <= wrdata_reg(0);
      ppsg_escr_sync_lw <= '1';
      ......@@ -493,6 +536,8 @@ begin
      ppsg_escr_nsec_set_int <= wrdata_reg(5);
      ppsg_escr_nsec_set_int_delay <= wrdata_reg(5);
      ppsg_escr_pps_in_term_int <= wrdata_reg(6);
      ppsg_escr_tod_in_term_int <= wrdata_reg(7);
      ppsg_escr_ext_tai_sync_int <= wrdata_reg(8);
      end if;
      if (wb_we_i = '0') then
      rddata_reg(0) <= 'X';
      ......@@ -507,7 +552,51 @@ begin
      rddata_reg(4) <= '0';
      rddata_reg(5) <= '0';
      rddata_reg(6) <= ppsg_escr_pps_in_term_int;
      rddata_reg(7) <= 'X';
      rddata_reg(7) <= ppsg_escr_tod_in_term_int;
      rddata_reg(8) <= ppsg_escr_ext_tai_sync_int;
      rddata_reg(9) <= ppsg_escr_ext_tai_ready_i;
      rddata_reg(10) <= 'X';
      rddata_reg(11) <= 'X';
      rddata_reg(12) <= 'X';
      rddata_reg(13) <= 'X';
      rddata_reg(14) <= 'X';
      rddata_reg(15) <= 'X';
      rddata_reg(16) <= 'X';
      rddata_reg(17) <= 'X';
      rddata_reg(18) <= 'X';
      rddata_reg(19) <= 'X';
      rddata_reg(20) <= 'X';
      rddata_reg(21) <= 'X';
      rddata_reg(22) <= 'X';
      rddata_reg(23) <= 'X';
      rddata_reg(24) <= 'X';
      rddata_reg(25) <= 'X';
      rddata_reg(26) <= 'X';
      rddata_reg(27) <= 'X';
      rddata_reg(28) <= 'X';
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "1000" =>
      if (wb_we_i = '1') then
      end if;
      if (wb_we_i = '0') then
      ppsg_ext_cntr_utclo_lwb <= '1';
      ppsg_ext_cntr_utclo_lwb_delay <= '1';
      ppsg_ext_cntr_utclo_lwb_in_progress <= '1';
      end if;
      ack_sreg(5) <= '1';
      ack_in_progress <= '1';
      when "1001" =>
      if (wb_we_i = '1') then
      end if;
      if (wb_we_i = '0') then
      ppsg_ext_cntr_utchi_lwb <= '1';
      ppsg_ext_cntr_utchi_lwb_delay <= '1';
      ppsg_ext_cntr_utchi_lwb_in_progress <= '1';
      end if;
      rddata_reg(8) <= 'X';
      rddata_reg(9) <= 'X';
      rddata_reg(10) <= 'X';
      ......@@ -830,8 +919,55 @@ begin
      -- Enable PPS_IN 50Ohm termination
      ppsg_escr_pps_in_term_o <= ppsg_escr_pps_in_term_int;
      -- Enable TOD IN 5OOhm termination
      ppsg_escr_tod_in_term_o <= ppsg_escr_tod_in_term_int;
      -- Set UTC counter to External UTC Input
      ppsg_escr_ext_tai_sync_o <= ppsg_escr_ext_tai_sync_int;
      -- External UTC Status
      -- UTC Counter
      -- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
      process (refclk_i, rst_n_i)
      begin
      if (rst_n_i = '0') then
      ppsg_ext_cntr_utclo_lwb_s0 <= '0';
      ppsg_ext_cntr_utclo_lwb_s1 <= '0';
      ppsg_ext_cntr_utclo_lwb_s2 <= '0';
      ppsg_ext_cntr_utclo_int <= "00000000000000000000000000000000";
      elsif rising_edge(refclk_i) then
      ppsg_ext_cntr_utclo_lwb_s0 <= ppsg_ext_cntr_utclo_lwb;
      ppsg_ext_cntr_utclo_lwb_s1 <= ppsg_ext_cntr_utclo_lwb_s0;
      ppsg_ext_cntr_utclo_lwb_s2 <= ppsg_ext_cntr_utclo_lwb_s1;
      if ((ppsg_ext_cntr_utclo_lwb_s1 = '1') and (ppsg_ext_cntr_utclo_lwb_s2 = '0')) then
      ppsg_ext_cntr_utclo_int <= ppsg_ext_cntr_utclo_i;
      end if;
      end if;
      end process;
      -- UTC Counter
      -- asynchronous std_logic_vector register : UTC Counter (type RO/WO, refclk_i <-> clk_sys_i)
      process (refclk_i, rst_n_i)
      begin
      if (rst_n_i = '0') then
      ppsg_ext_cntr_utchi_lwb_s0 <= '0';
      ppsg_ext_cntr_utchi_lwb_s1 <= '0';
      ppsg_ext_cntr_utchi_lwb_s2 <= '0';
      ppsg_ext_cntr_utchi_int <= "00000000";
      elsif rising_edge(refclk_i) then
      ppsg_ext_cntr_utchi_lwb_s0 <= ppsg_ext_cntr_utchi_lwb;
      ppsg_ext_cntr_utchi_lwb_s1 <= ppsg_ext_cntr_utchi_lwb_s0;
      ppsg_ext_cntr_utchi_lwb_s2 <= ppsg_ext_cntr_utchi_lwb_s1;
      if ((ppsg_ext_cntr_utchi_lwb_s1 = '1') and (ppsg_ext_cntr_utchi_lwb_s2 = '0')) then
      ppsg_ext_cntr_utchi_int <= ppsg_ext_cntr_utchi_i;
      end if;
      end if;
      end process;
      rwaddr_reg <= wb_adr_i;
      wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
      wb_err_o <= '0';
      wb_rty_o <= '0';
      -- ACK signal generation. Just pass the LSB of ACK counter.
      wb_ack_o <= ack_sreg(0);
      end syn;
      modules/wr_pps_gen/pps_gen_wb.wb
      View file @ 50d6bf22
      ......@@ -232,5 +232,69 @@ peripheral {
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "Enable TOD IN 5OOhm termination";
      description = "write 1: enable 50ohm termination for TOD input \
      write 0: disable 50ohm termination for TOD input \
      read 1: 50ohm termination for TOD input enabled \
      read 0: 50ohm termination for TOD input disabled";
      prefix = "TOD_IN_TERM";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "Set UTC counter to External UTC Input";
      description = "write 1: enable UTC counter to sync to External UTC Input.\
      write 0: disable UTC counter to sync to External UTC Input";
      prefix = "EXT_TAI_SYNC";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "External UTC Status";
      description = "read 1: External UTC is ready.\
      read 0: External UTC is not ready";
      prefix = "EXT_TAI_READY";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      };
      };
      reg {
      name = "EXT UTC Counter register (least-significant part)";
      description = "Lower 32 bits of current UTC time";
      prefix = "EXT_CNTR_UTCLO";
      field {
      name = "UTC Counter";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "refclk_i";
      };
      };
      reg {
      name = "EXT UTC Counter register (most-significant part)";
      description = "Highest 8 bits of current UTC time";
      prefix = "EXT_CNTR_UTCHI";
      field {
      name = "UTC Counter";
      type = SLV;
      size = 8;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "refclk_i";
      };
      };
      };
      modules/wr_pps_gen/wr_pps_gen.vhd
      View file @ 50d6bf22
      ......@@ -62,7 +62,7 @@ entity wr_pps_gen is
      rst_ref_n_i : in std_logic;
      rst_sys_n_i : in std_logic;
      wb_adr_i : in std_logic_vector(4 downto 0);
      wb_adr_i : in std_logic_vector(5 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -83,11 +83,18 @@ entity wr_pps_gen is
      ppsin_term_o : out std_logic;
      -- Single-pulse PPS output for synchronizing endpoints to
      pps_valid_int_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      ......@@ -105,7 +112,7 @@ architecture behavioral of wr_pps_gen is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(2 downto 0);
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -139,7 +146,12 @@ architecture behavioral of wr_pps_gen is
      ppsg_escr_sec_set_o : out std_logic;
      ppsg_escr_nsec_set_o : out std_logic;
      ppsg_escr_pps_unmask_o : out std_logic;
      ppsg_escr_pps_in_term_o: out std_logic);
      ppsg_escr_pps_in_term_o: out std_logic;
      ppsg_escr_tod_in_term_o : out std_logic;
      ppsg_escr_ext_tai_sync_o : out std_logic;
      ppsg_escr_ext_tai_ready_i: in std_logic;
      ppsg_ext_cntr_utclo_i : in std_logic_vector(31 downto 0);
      ppsg_ext_cntr_utchi_i : in std_logic_vector(7 downto 0));
      end component pps_gen_wb;
      -- Wisbone slave signals
      ......@@ -206,13 +218,18 @@ architecture behavioral of wr_pps_gen is
      signal pps_out_int : std_logic;
      signal pps_in_refclk : std_logic;
      signal set_ext_tai : std_logic;
      signal ext_tai : unsigned(39 downto 0);
      signal ppsg_escr_ext_tai_sync : std_logic;
      signal ppsg_escr_ext_tai_ready : std_logic;
      signal ppsg_ext_cntr_utclo : std_logic_vector(31 downto 0);
      signal ppsg_ext_cntr_utchi : std_logic_vector(7 downto 0);
      begin -- behavioral
      resized_addr(4 downto 0) <= wb_adr_i;
      resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
      resized_addr(5 downto 0) <= wb_adr_i;
      resized_addr(c_wishbone_address_width-1 downto 6) <= (others => '0');
      U_Adapter : wb_slave_adapter
      generic map (
      ......@@ -399,7 +416,9 @@ begin -- behavioral
      adjust_in_progress_utc <= '0';
      elsif(ppsg_cr_cnt_en = '1') then
      if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
      if(set_ext_tai = '1') then
      cntr_utc <= ext_tai;
      elsif(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
      cntr_utc <= adj_utc;
      elsif(cntr_adjust_p = '1') then
      adjust_in_progress_utc <= '1';
      ......@@ -465,7 +484,7 @@ begin -- behavioral
      port map (
      rst_n_i => rst_n_i,
      clk_sys_i => clk_sys_i,
      wb_adr_i => wb_in.adr(2 downto 0),
      wb_adr_i => wb_in.adr(3 downto 0),
      wb_dat_i => wb_in.dat,
      wb_dat_o => wb_out.dat,
      wb_cyc_i => wb_in.cyc,
      ......@@ -498,7 +517,12 @@ begin -- behavioral
      ppsg_escr_sec_set_o => ppsg_escr_sec_set,
      ppsg_escr_nsec_set_o => ppsg_escr_nsec_set,
      ppsg_escr_pps_unmask_o => ppsg_escr_pps_unmask,
      ppsg_escr_pps_in_term_o=> ppsin_term_o);
      ppsg_escr_pps_in_term_o=> ppsin_term_o,
      ppsg_escr_tod_in_term_o => todin_term_o,
      ppsg_escr_ext_tai_sync_o => ppsg_escr_ext_tai_sync,
      ppsg_escr_ext_tai_ready_i => ppsg_escr_ext_tai_ready,
      ppsg_ext_cntr_utclo_i => ppsg_ext_cntr_utclo,
      ppsg_ext_cntr_utchi_i => ppsg_ext_cntr_utchi);
      -- drive unused signals
      wb_out.rty <= '0';
      ......@@ -511,10 +535,63 @@ begin -- behavioral
      -- drive the readout value of CNT_ADJ to 1 when the adjustment is over
      ppsg_cr_cnt_adj_i <= pps_valid_int;
      pps_valid_o <= pps_valid_int;
      pps_valid_int_o <= pps_valid_int;
      pps_valid_o <= ppsg_escr_pps_valid;
      tm_utc_o <= std_logic_vector(cntr_utc);
      tm_cycles_o <= std_logic_vector(cntr_nsec);
      tm_time_valid_o <= ppsg_escr_tm_valid;
      pps_unmask_o <= ppsg_escr_pps_unmask;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_escr_ext_tai_ready <= '0';
      elsif(set_ext_tai = '1')then
      ppsg_escr_ext_tai_ready <= '1';
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_ext_cntr_utclo <= (others => '0');
      elsif(ext_tai_valid_p_i = '1') then
      ppsg_ext_cntr_utclo <= ext_tai_i(31 downto 0);
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_ext_cntr_utchi <= (others => '0');
      elsif(ext_tai_valid_p_i = '1') then
      ppsg_ext_cntr_utchi <= ext_tai_i(39 downto 32);
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      ext_tai <= unsigned(ext_tai_i);
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if((ext_tai_valid_p_i = '1') and (ext_tai_ready_i = '1') and (ppsg_escr_ext_tai_sync = '1')) then
      set_ext_tai <= '1';
      else
      set_ext_tai <= '0';
      end if;
      end if;
      end process;
      end behavioral;
      modules/wr_pps_gen/xwr_pps_gen.vhd
      View file @ 50d6bf22
      ......@@ -71,10 +71,17 @@ entity xwr_pps_gen is
      -- Single-pulse PPS output for synchronizing endpoints to
      pps_csync_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      ......@@ -98,7 +105,7 @@ architecture behavioral of xwr_pps_gen is
      clk_sys_i : in std_logic;
      rst_ref_n_i : in std_logic;
      rst_sys_n_i : in std_logic;
      wb_adr_i : in std_logic_vector(4 downto 0);
      wb_adr_i : in std_logic_vector(5 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -114,6 +121,12 @@ architecture behavioral of xwr_pps_gen is
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      tm_time_valid_o : out std_logic
      ......@@ -136,7 +149,7 @@ begin -- behavioral
      clk_sys_i => clk_sys_i,
      rst_ref_n_i => rst_ref_n_i,
      rst_sys_n_i => rst_sys_n_i,
      wb_adr_i => slave_i.adr(4 downto 0),
      wb_adr_i => slave_i.adr(5 downto 0),
      wb_dat_i => slave_i.dat,
      wb_dat_o => slave_o.dat,
      wb_cyc_i => slave_i.cyc,
      ......@@ -149,9 +162,15 @@ begin -- behavioral
      pps_in_i => pps_in_i,
      ppsin_term_o => ppsin_term_o,
      pps_csync_o => pps_csync_o,
      pps_valid_int_o => pps_valid_int_o,
      pps_out_o => pps_out_o,
      pps_led_o => pps_led_o,
      pps_valid_o => pps_valid_o,
      pps_unmask_o => pps_unmask_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      tm_utc_o => tm_utc_o,
      tm_cycles_o => tm_cycles_o,
      tm_time_valid_o => tm_time_valid_o
      ......
      modules/wr_sma_config/build_wb.sh 0 → 100755
      View file @ 50d6bf22
      #!/bin/bash
      mkdir -p doc
      /home/fpga/workspace/wr-tool/wishbone-gen/wbgen2 -D ./doc/sma_config.html -C sma_config_regs.h -V sma_config_wb_slave.vhd -p sma_config_wbgen2_pkg.vhd --cstyle struct --lang vhdl -H record sma_config.wb
      board/cute_a7/wr_fdelay_ctrl.vhd → modules/wr_sma_config/fine_delay_ctrl.vhd
      View file @ 50d6bf22
      ......@@ -2,37 +2,51 @@ library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      entity wr_fdelay_ctrl is
      library work;
      use work.gencores_pkg.all;
      use work.wishbone_pkg.all;
      entity fine_delay_ctrl is
      generic (
      fdelay_ch0 : std_logic_vector(8 downto 0) := (others=>'0');
      fdelay_ch1 : std_logic_vector(8 downto 0) := (others=>'0'));
      g_project_name : string := "NORMAL"
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      fine_dly_req_i : in std_logic;
      fine_dly_sel_i : in std_logic;
      fine_dly_values_i : in std_logic_vector(8 downto 0);
      fine_dly_busy_o : out std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end wr_fdelay_ctrl;
      end fine_delay_ctrl;
      architecture struct of wr_fdelay_ctrl is
      architecture struct of fine_delay_ctrl is
      constant c_fdelay_ch0 : std_logic_vector(8 downto 0) :="000001010";
      constant c_fdelay_ch1 : std_logic_vector(8 downto 0) :=(others=>'0');
      type fdly_ctrl_state is (S_IDLE, S_START_CONF_CH0, S_CONFIG_CH0, S_SPI_TRANS_CHO, S_CONFIG_DONE_CH0, S_FINISH_CH0, S_START_CONF_CH1, S_CONFIG_CH1, S_SPI_TRANS_CH1, S_CONFIG_DONE_CH1, S_FINISH_CH1);
      type fdly_ctrl_state is (S_IDLE,S_CONFIG_EN,S_SPI_LOAD,S_SPI_TRANS,S_SPI_END);
      signal delay_en : std_logic;
      signal delay_sload : std_logic;
      signal delay_sdin : std_logic;
      signal delay_sclk : std_logic;
      signal fine_dly_busy : std_logic;
      signal channel_sel : std_logic:='0';
      signal fine_dly : std_logic_vector(8 downto 0):=(others=>'0');
      signal spi_data : std_logic_vector(10 downto 0):=(others=>'0');
      begin
      signal delay_en :std_logic;
      signal delay_sload :std_logic;
      signal delay_sdin :std_logic;
      signal delay_sclk :std_logic;
      signal spi_data : std_logic_vector(10 downto 0):=(others=>'0');
      delay_en_o <= delay_en;
      delay_sload_o <= delay_sload;
      delay_sdin_o <= delay_sdin;
      delay_sclk_o <= delay_sclk;
      fine_dly_busy_o <= fine_dly_busy;
      begin
      P_FINE_DELAY_SPI: process(clk_sys_i)
      variable state : fdly_ctrl_state := S_IDLE;
      variable spi_cnt: natural range 0 to 12;
      ......@@ -40,83 +54,58 @@ begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n_i='0') then
      spi_data <= (others=>'0');
      delay_en <= '0';
      channel_sel <= '0';
      delay_sload <= '0';
      delay_sdin <= '0';
      delay_sclk <= '0';
      delay_en <= '0';
      fine_dly_busy <= '0';
      spi_cnt := 0;
      state := S_IDLE;
      else
      case(state) is
      when S_IDLE =>
      spi_data <= (others=>'0');
      delay_en <= '0';
      delay_sload <= '0';
      delay_sdin <= '0';
      delay_sclk <= '0';
      spi_cnt := 0;
      state := S_START_CONF_CH0;
      when S_START_CONF_CH0 =>
      delay_en <= '1';
      spi_data <= c_fdelay_ch0 & '0' & '0';
      state := S_CONFIG_CH0;
      when S_CONFIG_CH0 =>
      delay_sdin <= spi_data(0);
      delay_sclk <= '0';
      state := S_SPI_TRANS_CHO;
      if(spi_cnt = 11) then
      delay_sload <= '1';
      state := S_CONFIG_DONE_CH0;
      end if;
      when S_SPI_TRANS_CHO =>
      spi_data <= '0' & spi_data(10 downto 1);
      delay_sclk <= '1';
      spi_cnt := spi_cnt + 1;
      state := S_CONFIG_CH0;
      when S_CONFIG_DONE_CH0 =>
      channel_sel <= '0';
      fine_dly <= (others=>'0');
      spi_data <= (others=>'0');
      delay_en <= '0';
      delay_sload <= '0';
      spi_data <= fdelay_ch1 & '0' & '1';
      delay_sdin <= '0';
      delay_sclk <= '0';
      fine_dly_busy <= '0';
      spi_cnt := 0;
      state := S_FINISH_CH0;
      when S_FINISH_CH0 =>
      delay_en <= '0';
      state := S_START_CONF_CH1;
      if (fine_dly_req_i='1') then
      fine_dly <= fine_dly_values_i;
      channel_sel <= fine_dly_sel_i;
      fine_dly_busy <= '1';
      state := S_CONFIG_EN;
      end if;
      when S_START_CONF_CH1 =>
      delay_en <= '1';
      spi_data <= c_fdelay_ch1 & '0' & '1';
      state := S_CONFIG_CH1;
      when S_CONFIG_EN =>
      spi_data <= fine_dly & '0' & channel_sel;
      delay_en <= '1';
      state := S_SPI_LOAD;
      when S_CONFIG_CH1 =>
      when S_SPI_LOAD =>
      delay_sdin <= spi_data(0);
      delay_sclk <= '0';
      state := S_SPI_TRANS_CH1;
      state := S_SPI_TRANS;
      if(spi_cnt = 11) then
      delay_sload <= '1';
      state := S_CONFIG_DONE_CH1;
      state := S_SPI_END;
      end if;
      when S_SPI_TRANS_CH1 =>
      when S_SPI_TRANS =>
      spi_data <= '0' & spi_data(10 downto 1);
      delay_sclk <= '1';
      spi_cnt := spi_cnt + 1;
      state := S_CONFIG_CH1;
      state := S_SPI_LOAD;
      when S_CONFIG_DONE_CH1 =>
      when S_SPI_END =>
      delay_sload <= '0';
      spi_data <= (others => '0');
      spi_cnt := 0;
      state := S_FINISH_CH1;
      when S_FINISH_CH1 =>
      delay_en <= '0';
      state := S_FINISH_CH1;
      delay_en <= '0';
      state := S_IDLE;
      fine_dly_busy <= '0';
      when others =>
      state := S_IDLE;
      ......@@ -125,10 +114,5 @@ begin
      end if;
      end process P_FINE_DELAY_SPI;
      delay_en_o <= delay_en;
      delay_sload_o <= delay_sload;
      delay_sdin_o <= delay_sdin;
      delay_sclk_o <= delay_sclk;
      end struct;
      modules/wr_sma_config/oserdes_8_to_1.v 0 → 100644
      View file @ 50d6bf22
      // file: selectio_wiz_0_selectio_wiz.v
      // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
      //
      // This file contains confidential and proprietary information
      // of Xilinx, Inc. and is protected under U.S. and
      // international copyright and other intellectual property
      // laws.
      //
      // DISCLAIMER
      // This disclaimer is not a license and does not grant any
      // rights to the materials distributed herewith. Except as
      // otherwise provided in a valid license issued to you by
      // Xilinx, and to the maximum extent permitted by applicable
      // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
      // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
      // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
      // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
      // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
      // (2) Xilinx shall not be liable (whether in contract or tort,
      // including negligence, or under any other theory of
      // liability) for any loss or damage of any kind or nature
      // related to, arising under or in connection with these
      // materials, including for any direct, or any indirect,
      // special, incidental, or consequential loss or damage
      // (including loss of data, profits, goodwill, or any type of
      // loss or damage suffered as a result of any action brought
      // by a third party) even if such damage or loss was
      // reasonably foreseeable or Xilinx had been advised of the
      // possibility of the same.
      //
      // CRITICAL APPLICATIONS
      // Xilinx products are not designed or intended to be fail-
      // safe, or for use in any application requiring fail-safe
      // performance, such as life-support or safety devices or
      // systems, Class III medical devices, nuclear facilities,
      // applications related to the deployment of airbags, or any
      // other applications that could lead to death, personal
      // injury, or severe property or environmental damage
      // (individually and collectively, "Critical
      // Applications"). Customer assumes the sole risk and
      // liability of any use of Xilinx products in Critical
      // Applications, subject only to applicable laws and
      // regulations governing limitations on product liability.
      //
      // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
      // PART OF THIS FILE AT ALL TIMES.
      //----------------------------------------------------------------------------
      // User entered comments
      //----------------------------------------------------------------------------
      // None
      //----------------------------------------------------------------------------
      `timescale 1ps/1ps
      module oserdes_8_to_1
      // width of the data for the system
      #(parameter SYS_W = 1,
      // width of the data for the device
      parameter DEV_W = 8)
      (
      // From the device out to the system
      input [DEV_W-1:0] data_out_from_device,
      output [SYS_W-1:0] data_out_to_pins_p,
      output [SYS_W-1:0] data_out_to_pins_n,
      input clk_in, // Fast clock input from PLL/MMCM
      input clk_div_in, // Slow clock input from PLL/MMCM
      input io_reset);
      localparam num_serial_bits = DEV_W/SYS_W;
      wire clock_enable = 1'b1;
      // Signal declarations
      ////------------------------------
      // Before the buffer
      wire [SYS_W-1:0] data_out_to_pins_int;
      // Between the delay and serdes
      wire [SYS_W-1:0] data_out_to_pins_predelay;
      // Array to use intermediately from the serdes to the internal
      // devices. bus "0" is the leftmost bus
      wire [SYS_W-1:0] oserdes_d[0:13]; // fills in starting with 13
      // Create the clock logic
      // We have multiple bits- step over every bit, instantiating the required elements
      genvar pin_count;
      genvar slice_count;
      generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins
      // Instantiate the buffers
      ////------------------------------
      // Instantiate a buffer for every bit of the data bus
      OBUFDS
      #(.IOSTANDARD ("LVDS_25"))
      obufds_inst
      (.O (data_out_to_pins_p [pin_count]),
      .OB (data_out_to_pins_n [pin_count]),
      .I (data_out_to_pins_int[pin_count]));
      // Pass through the delay
      ////-------------------------------
      assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count];
      // Instantiate the serdes primitive
      ////------------------------------
      // declare the oserdes
      OSERDESE2
      # (
      .DATA_RATE_OQ ("SDR"),
      .DATA_RATE_TQ ("SDR"),
      .DATA_WIDTH (8),
      .TRISTATE_WIDTH (1),
      .SERDES_MODE ("MASTER"))
      oserdese2_master (
      .D1 (oserdes_d[13][pin_count]),
      .D2 (oserdes_d[12][pin_count]),
      .D3 (oserdes_d[11][pin_count]),
      .D4 (oserdes_d[10][pin_count]),
      .D5 (oserdes_d[9][pin_count]),
      .D6 (oserdes_d[8][pin_count]),
      .D7 (oserdes_d[7][pin_count]),
      .D8 (oserdes_d[6][pin_count]),
      .T1 (1'b0),
      .T2 (1'b0),
      .T3 (1'b0),
      .T4 (1'b0),
      .SHIFTIN1 (1'b0),
      .SHIFTIN2 (1'b0),
      .SHIFTOUT1 (),
      .SHIFTOUT2 (),
      .OCE (clock_enable),
      .CLK (clk_in),
      .CLKDIV (clk_div_in),
      .OQ (data_out_to_pins_predelay[pin_count]),
      .TQ (),
      .OFB (),
      .TFB (),
      .TBYTEIN (1'b0),
      .TBYTEOUT (),
      .TCE (1'b0),
      .RST (io_reset));
      // Concatenate the serdes outputs together. Keep the timesliced
      // bits together, and placing the earliest bits on the right
      // ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
      // the output will be 3210, 7654, ...
      ////---------------------------------------------------------
      for (slice_count = 0; slice_count < num_serial_bits; slice_count = slice_count + 1) begin: out_slices
      // This places the first data in time on the right
      assign oserdes_d[14-slice_count-1] =
      data_out_from_device[slice_count];
      // To place the first data in time on the left, use the
      // following code, instead
      // assign oserdes_d[slice_count] =
      // data_out_from_device[slice_count];
      end
      end
      endgenerate
      endmodule
      modules/wr_sma_config/sma_config.wb 0 → 100644
      View file @ 50d6bf22
      -- -*- Mode: LUA; tab-width: 2 -*-
      -- CUTE-WR-A7 SMA Output Control
      --
      -- Use wbgen2 to generate code, documentation and more.
      -- wbgen2 is available at:
      -- http://www.ohwr.org/projects/wishbone-gen
      --
      peripheral {
      name = "WR aux sma output generation module";
      description = "The module allows gerating WR-aligned signal including PPS/mPPS/\
      UTC Coding and other signal of a given frequency, duty cycle and phase. \
      The output signals of two SMA interfaces can be configured. \
      The fine delay chip can also be configured via this module.\
      The By default it is configured to generate 10MHz signal and PPS.";
      hdl_entity = "sma_config_wb";
      prefix = "sma_config";
      reg {
      name = "SMA0 MUX";
      prefix = "SMA0";
      field {
      name = "SMA0 Signal Selection";
      description = "Select the signal of SMA0.\
      0: UTC Coding\
      1: Customed Frequency.";
      prefix = "MUX";
      size = 8;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA1 MUX";
      prefix = "SMA1";
      field {
      name = "SMA1 Signal Selection";
      description = "Select the signal of SMA1.\
      0: UTC Coding\
      1: Customed Frequency.";
      prefix = "MUX";
      size = 8;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Period Register : High State";
      prefix = "CUS_PRH";
      field {
      name = "High state length";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Period Register : Low State";
      prefix = "CUS_PRL";
      field {
      name = "Low state width";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Coarse Shift Register";
      prefix = "CUS_CSR";
      field {
      name = "Coarse shift value in 2ns cycles.";
      description = "MUST be not larger than the required clock period";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "PPS Period High Register";
      prefix = "PPS_PRH";
      field {
      name = "High state width";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "PPS Coarse Shift Register";
      prefix = "PPS_CSR";
      field {
      name = "Coarse shift value";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "UTC Coding Coarse Shift Register";
      prefix = "UTC_CSR";
      field {
      name = "Coarse shift value";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA0 Fine Delays Register";
      prefix = "SMA0_FDLY";
      field {
      name = "fine delay counter";
      description = "delay chip value to SMA0 signals";
      type = SLV;
      size = 9;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA1 Fine Delays Register";
      prefix = "SMA1_FDLY";
      field {
      name = "fine delay counter";
      description = "delay chip value to SMA1 signals";
      type = SLV;
      size = 9;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      }
      modules/wr_sma_config/sma_config_pkg.vhd 0 → 100644
      View file @ 50d6bf22
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      library work;
      use work.wishbone_pkg.all;
      use work.sma_config_wbgen2_pkg.all;
      package sma_config_pkg is
      constant c_DATA_W : integer := 8; -- parallel data width going to serdes
      constant c_HALF : integer := 25;-- default high/low width for 10MHz
      component sma_config_wb is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      wb_sel_i : in std_logic_vector(3 downto 0);
      wb_stb_i : in std_logic;
      wb_we_i : in std_logic;
      wb_ack_o : out std_logic;
      wb_stall_o : out std_logic;
      regs_i : in t_sma_config_in_registers;
      regs_o : out t_sma_config_out_registers
      );
      end component;
      component oserdes_8_to_1 is
      generic(
      sys_w : integer := 1;
      dev_w : integer := 8);
      port(
      DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
      DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
      DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
      CLK_IN : in std_logic;
      CLK_DIV_IN : in std_logic;
      IO_RESET : in std_logic);
      end component;
      component fine_delay_ctrl is
      generic (
      g_project_name : string := "NORMAL"
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      fine_dly_req_i : in std_logic;
      fine_dly_sel_i : in std_logic;
      fine_dly_values_i : in std_logic_vector(8 downto 0);
      fine_dly_busy_o : out std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end component;
      component utc_coding is
      port(
      clk_ref_i : in std_logic;
      rst_n_i : in std_logic;
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_utc_i : in std_logic_vector(39 downto 0);
      tm_serial_o : out std_logic
      );
      end component;
      end package;
      --package body shine_config_pkg is
      --end package body;
      modules/wr_sma_config/sma_config_wb_slave.vhd 0 → 100644
      View file @ 50d6bf22
      ---------------------------------------------------------------------------------------
      -- Title : Wishbone slave core for WR aux sma output generation module
      ---------------------------------------------------------------------------------------
      -- File : sma_config_wb_slave.vhd
      -- Author : auto-generated by wbgen2 from sma_config.wb
      -- Created : Mon Oct 17 22:55:06 2022
      -- Standard : VHDL'87
      ---------------------------------------------------------------------------------------
      -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sma_config.wb
      -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
      ---------------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      use work.sma_config_wbgen2_pkg.all;
      entity sma_config_wb is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      wb_sel_i : in std_logic_vector(3 downto 0);
      wb_stb_i : in std_logic;
      wb_we_i : in std_logic;
      wb_ack_o : out std_logic;
      wb_stall_o : out std_logic;
      regs_i : in t_sma_config_in_registers;
      regs_o : out t_sma_config_out_registers
      );
      end sma_config_wb;
      architecture syn of sma_config_wb is
      signal ack_sreg : std_logic_vector(9 downto 0);
      signal rddata_reg : std_logic_vector(31 downto 0);
      signal wrdata_reg : std_logic_vector(31 downto 0);
      signal bwsel_reg : std_logic_vector(3 downto 0);
      signal rwaddr_reg : std_logic_vector(3 downto 0);
      signal ack_in_progress : std_logic ;
      signal wr_int : std_logic ;
      signal rd_int : std_logic ;
      signal allones : std_logic_vector(31 downto 0);
      signal allzeros : std_logic_vector(31 downto 0);
      begin
      -- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
      wrdata_reg <= wb_dat_i;
      bwsel_reg <= wb_sel_i;
      rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
      wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
      allones <= (others => '1');
      allzeros <= (others => '0');
      --
      -- Main register bank access process.
      process (clk_sys_i, rst_n_i)
      begin
      if (rst_n_i = '0') then
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      regs_o.sma0_mux_load_o <= '0';
      regs_o.sma1_mux_load_o <= '0';
      regs_o.cus_prh_load_o <= '0';
      regs_o.cus_prl_load_o <= '0';
      regs_o.cus_csr_load_o <= '0';
      regs_o.pps_prh_load_o <= '0';
      regs_o.pps_csr_load_o <= '0';
      regs_o.utc_csr_load_o <= '0';
      regs_o.sma0_fdly_load_o <= '0';
      regs_o.sma1_fdly_load_o <= '0';
      elsif rising_edge(clk_sys_i) then
      -- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
      if (ack_sreg(0) = '1') then
      regs_o.sma0_mux_load_o <= '0';
      regs_o.sma1_mux_load_o <= '0';
      regs_o.cus_prh_load_o <= '0';
      regs_o.cus_prl_load_o <= '0';
      regs_o.cus_csr_load_o <= '0';
      regs_o.pps_prh_load_o <= '0';
      regs_o.pps_csr_load_o <= '0';
      regs_o.utc_csr_load_o <= '0';
      regs_o.sma0_fdly_load_o <= '0';
      regs_o.sma1_fdly_load_o <= '0';
      ack_in_progress <= '0';
      else
      regs_o.sma0_mux_load_o <= '0';
      regs_o.sma1_mux_load_o <= '0';
      regs_o.cus_prh_load_o <= '0';
      regs_o.cus_prl_load_o <= '0';
      regs_o.cus_csr_load_o <= '0';
      regs_o.pps_prh_load_o <= '0';
      regs_o.pps_csr_load_o <= '0';
      regs_o.utc_csr_load_o <= '0';
      regs_o.sma0_fdly_load_o <= '0';
      regs_o.sma1_fdly_load_o <= '0';
      end if;
      else
      if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
      case rwaddr_reg(3 downto 0) is
      when "0000" =>
      if (wb_we_i = '1') then
      regs_o.sma0_mux_load_o <= '1';
      end if;
      rddata_reg(7 downto 0) <= regs_i.sma0_mux_i;
      rddata_reg(8) <= 'X';
      rddata_reg(9) <= 'X';
      rddata_reg(10) <= 'X';
      rddata_reg(11) <= 'X';
      rddata_reg(12) <= 'X';
      rddata_reg(13) <= 'X';
      rddata_reg(14) <= 'X';
      rddata_reg(15) <= 'X';
      rddata_reg(16) <= 'X';
      rddata_reg(17) <= 'X';
      rddata_reg(18) <= 'X';
      rddata_reg(19) <= 'X';
      rddata_reg(20) <= 'X';
      rddata_reg(21) <= 'X';
      rddata_reg(22) <= 'X';
      rddata_reg(23) <= 'X';
      rddata_reg(24) <= 'X';
      rddata_reg(25) <= 'X';
      rddata_reg(26) <= 'X';
      rddata_reg(27) <= 'X';
      rddata_reg(28) <= 'X';
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0001" =>
      if (wb_we_i = '1') then
      regs_o.sma1_mux_load_o <= '1';
      end if;
      rddata_reg(7 downto 0) <= regs_i.sma1_mux_i;
      rddata_reg(8) <= 'X';
      rddata_reg(9) <= 'X';
      rddata_reg(10) <= 'X';
      rddata_reg(11) <= 'X';
      rddata_reg(12) <= 'X';
      rddata_reg(13) <= 'X';
      rddata_reg(14) <= 'X';
      rddata_reg(15) <= 'X';
      rddata_reg(16) <= 'X';
      rddata_reg(17) <= 'X';
      rddata_reg(18) <= 'X';
      rddata_reg(19) <= 'X';
      rddata_reg(20) <= 'X';
      rddata_reg(21) <= 'X';
      rddata_reg(22) <= 'X';
      rddata_reg(23) <= 'X';
      rddata_reg(24) <= 'X';
      rddata_reg(25) <= 'X';
      rddata_reg(26) <= 'X';
      rddata_reg(27) <= 'X';
      rddata_reg(28) <= 'X';
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0010" =>
      if (wb_we_i = '1') then
      regs_o.cus_prh_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.cus_prh_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0011" =>
      if (wb_we_i = '1') then
      regs_o.cus_prl_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.cus_prl_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0100" =>
      if (wb_we_i = '1') then
      regs_o.cus_csr_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.cus_csr_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0101" =>
      if (wb_we_i = '1') then
      regs_o.pps_prh_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.pps_prh_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0110" =>
      if (wb_we_i = '1') then
      regs_o.pps_csr_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.pps_csr_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "0111" =>
      if (wb_we_i = '1') then
      regs_o.utc_csr_load_o <= '1';
      end if;
      rddata_reg(28 downto 0) <= regs_i.utc_csr_i;
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "1000" =>
      if (wb_we_i = '1') then
      regs_o.sma0_fdly_load_o <= '1';
      end if;
      rddata_reg(8 downto 0) <= regs_i.sma0_fdly_i;
      rddata_reg(9) <= 'X';
      rddata_reg(10) <= 'X';
      rddata_reg(11) <= 'X';
      rddata_reg(12) <= 'X';
      rddata_reg(13) <= 'X';
      rddata_reg(14) <= 'X';
      rddata_reg(15) <= 'X';
      rddata_reg(16) <= 'X';
      rddata_reg(17) <= 'X';
      rddata_reg(18) <= 'X';
      rddata_reg(19) <= 'X';
      rddata_reg(20) <= 'X';
      rddata_reg(21) <= 'X';
      rddata_reg(22) <= 'X';
      rddata_reg(23) <= 'X';
      rddata_reg(24) <= 'X';
      rddata_reg(25) <= 'X';
      rddata_reg(26) <= 'X';
      rddata_reg(27) <= 'X';
      rddata_reg(28) <= 'X';
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when "1001" =>
      if (wb_we_i = '1') then
      regs_o.sma1_fdly_load_o <= '1';
      end if;
      rddata_reg(8 downto 0) <= regs_i.sma1_fdly_i;
      rddata_reg(9) <= 'X';
      rddata_reg(10) <= 'X';
      rddata_reg(11) <= 'X';
      rddata_reg(12) <= 'X';
      rddata_reg(13) <= 'X';
      rddata_reg(14) <= 'X';
      rddata_reg(15) <= 'X';
      rddata_reg(16) <= 'X';
      rddata_reg(17) <= 'X';
      rddata_reg(18) <= 'X';
      rddata_reg(19) <= 'X';
      rddata_reg(20) <= 'X';
      rddata_reg(21) <= 'X';
      rddata_reg(22) <= 'X';
      rddata_reg(23) <= 'X';
      rddata_reg(24) <= 'X';
      rddata_reg(25) <= 'X';
      rddata_reg(26) <= 'X';
      rddata_reg(27) <= 'X';
      rddata_reg(28) <= 'X';
      rddata_reg(29) <= 'X';
      rddata_reg(30) <= 'X';
      rddata_reg(31) <= 'X';
      ack_sreg(0) <= '1';
      ack_in_progress <= '1';
      when others =>
      -- prevent the slave from hanging the bus on invalid address
      ack_in_progress <= '1';
      ack_sreg(0) <= '1';
      end case;
      end if;
      end if;
      end if;
      end process;
      -- Drive the data output bus
      wb_dat_o <= rddata_reg;
      -- SMA0 Signal Selection
      regs_o.sma0_mux_o <= wrdata_reg(7 downto 0);
      -- SMA1 Signal Selection
      regs_o.sma1_mux_o <= wrdata_reg(7 downto 0);
      -- High state length
      regs_o.cus_prh_o <= wrdata_reg(28 downto 0);
      -- Low state width
      regs_o.cus_prl_o <= wrdata_reg(28 downto 0);
      -- Coarse shift value in 2ns cycles.
      regs_o.cus_csr_o <= wrdata_reg(28 downto 0);
      -- High state width
      regs_o.pps_prh_o <= wrdata_reg(28 downto 0);
      -- Coarse shift value
      regs_o.pps_csr_o <= wrdata_reg(28 downto 0);
      -- Coarse shift value
      regs_o.utc_csr_o <= wrdata_reg(28 downto 0);
      -- fine delay counter
      regs_o.sma0_fdly_o <= wrdata_reg(8 downto 0);
      -- fine delay counter
      regs_o.sma1_fdly_o <= wrdata_reg(8 downto 0);
      rwaddr_reg <= wb_adr_i;
      wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
      -- ACK signal generation. Just pass the LSB of ACK counter.
      wb_ack_o <= ack_sreg(0);
      end syn;
      modules/wr_sma_config/sma_config_wbgen2_pkg.vhd 0 → 100644
      View file @ 50d6bf22
      ---------------------------------------------------------------------------------------
      -- Title : Wishbone slave core for WR aux sma output generation module
      ---------------------------------------------------------------------------------------
      -- File : sma_config_wbgen2_pkg.vhd
      -- Author : auto-generated by wbgen2 from sma_config.wb
      -- Created : Mon Oct 17 22:55:06 2022
      -- Standard : VHDL'87
      ---------------------------------------------------------------------------------------
      -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sma_config.wb
      -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
      ---------------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      package sma_config_wbgen2_pkg is
      -- Input registers (user design -> WB slave)
      type t_sma_config_in_registers is record
      sma0_mux_i : std_logic_vector(7 downto 0);
      sma1_mux_i : std_logic_vector(7 downto 0);
      cus_prh_i : std_logic_vector(28 downto 0);
      cus_prl_i : std_logic_vector(28 downto 0);
      cus_csr_i : std_logic_vector(28 downto 0);
      pps_prh_i : std_logic_vector(28 downto 0);
      pps_csr_i : std_logic_vector(28 downto 0);
      utc_csr_i : std_logic_vector(28 downto 0);
      sma0_fdly_i : std_logic_vector(8 downto 0);
      sma1_fdly_i : std_logic_vector(8 downto 0);
      end record;
      constant c_sma_config_in_registers_init_value: t_sma_config_in_registers := (
      sma0_mux_i => (others => '0'),
      sma1_mux_i => (others => '0'),
      cus_prh_i => (others => '0'),
      cus_prl_i => (others => '0'),
      cus_csr_i => (others => '0'),
      pps_prh_i => (others => '0'),
      pps_csr_i => (others => '0'),
      utc_csr_i => (others => '0'),
      sma0_fdly_i => (others => '0'),
      sma1_fdly_i => (others => '0')
      );
      -- Output registers (WB slave -> user design)
      type t_sma_config_out_registers is record
      sma0_mux_o : std_logic_vector(7 downto 0);
      sma0_mux_load_o : std_logic;
      sma1_mux_o : std_logic_vector(7 downto 0);
      sma1_mux_load_o : std_logic;
      cus_prh_o : std_logic_vector(28 downto 0);
      cus_prh_load_o : std_logic;
      cus_prl_o : std_logic_vector(28 downto 0);
      cus_prl_load_o : std_logic;
      cus_csr_o : std_logic_vector(28 downto 0);
      cus_csr_load_o : std_logic;
      pps_prh_o : std_logic_vector(28 downto 0);
      pps_prh_load_o : std_logic;
      pps_csr_o : std_logic_vector(28 downto 0);
      pps_csr_load_o : std_logic;
      utc_csr_o : std_logic_vector(28 downto 0);
      utc_csr_load_o : std_logic;
      sma0_fdly_o : std_logic_vector(8 downto 0);
      sma0_fdly_load_o : std_logic;
      sma1_fdly_o : std_logic_vector(8 downto 0);
      sma1_fdly_load_o : std_logic;
      end record;
      constant c_sma_config_out_registers_init_value: t_sma_config_out_registers := (
      sma0_mux_o => (others => '0'),
      sma0_mux_load_o => '0',
      sma1_mux_o => (others => '0'),
      sma1_mux_load_o => '0',
      cus_prh_o => (others => '0'),
      cus_prh_load_o => '0',
      cus_prl_o => (others => '0'),
      cus_prl_load_o => '0',
      cus_csr_o => (others => '0'),
      cus_csr_load_o => '0',
      pps_prh_o => (others => '0'),
      pps_prh_load_o => '0',
      pps_csr_o => (others => '0'),
      pps_csr_load_o => '0',
      utc_csr_o => (others => '0'),
      utc_csr_load_o => '0',
      sma0_fdly_o => (others => '0'),
      sma0_fdly_load_o => '0',
      sma1_fdly_o => (others => '0'),
      sma1_fdly_load_o => '0'
      );
      function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers;
      function f_x_to_zero (x:std_logic) return std_logic;
      function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
      end package;
      package body sma_config_wbgen2_pkg is
      function f_x_to_zero (x:std_logic) return std_logic is
      begin
      if x = '1' then
      return '1';
      else
      return '0';
      end if;
      end function;
      function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
      variable tmp: std_logic_vector(x'length-1 downto 0);
      begin
      for i in 0 to x'length-1 loop
      if(x(i) = 'X' or x(i) = 'U') then
      tmp(i):= '0';
      else
      tmp(i):=x(i);
      end if;
      end loop;
      return tmp;
      end function;
      function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers is
      variable tmp: t_sma_config_in_registers;
      begin
      tmp.sma0_mux_i := f_x_to_zero(left.sma0_mux_i) or f_x_to_zero(right.sma0_mux_i);
      tmp.sma1_mux_i := f_x_to_zero(left.sma1_mux_i) or f_x_to_zero(right.sma1_mux_i);
      tmp.cus_prh_i := f_x_to_zero(left.cus_prh_i) or f_x_to_zero(right.cus_prh_i);
      tmp.cus_prl_i := f_x_to_zero(left.cus_prl_i) or f_x_to_zero(right.cus_prl_i);
      tmp.cus_csr_i := f_x_to_zero(left.cus_csr_i) or f_x_to_zero(right.cus_csr_i);
      tmp.pps_prh_i := f_x_to_zero(left.pps_prh_i) or f_x_to_zero(right.pps_prh_i);
      tmp.pps_csr_i := f_x_to_zero(left.pps_csr_i) or f_x_to_zero(right.pps_csr_i);
      tmp.utc_csr_i := f_x_to_zero(left.utc_csr_i) or f_x_to_zero(right.utc_csr_i);
      tmp.sma0_fdly_i := f_x_to_zero(left.sma0_fdly_i) or f_x_to_zero(right.sma0_fdly_i);
      tmp.sma1_fdly_i := f_x_to_zero(left.sma1_fdly_i) or f_x_to_zero(right.sma1_fdly_i);
      return tmp;
      end function;
      end package body;
      modules/wr_sma_config/utc_coding.vhd 0 → 100644
      View file @ 50d6bf22
      Library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      entity utc_coding is
      port(
      clk_ref_i : in std_logic;
      rst_n_i : in std_logic;
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_utc_i : in std_logic_vector(39 downto 0);
      tm_serial_o : out std_logic
      );
      end utc_coding;
      Architecture beha of utc_coding is
      type t_state is (idle, wt_utc, tx_utc);
      signal state : t_state;
      signal cnt : unsigned(5 downto 0);
      signal tm_utc_int : std_logic_vector(39 downto 0);
      begin
      p_tm_serial : process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_n_i = '0' then
      tm_serial_o <= '0';
      cnt <= (others => '0');
      state <= idle;
      tm_utc_int <= (others => '0');
      else
      case state is
      when idle =>
      if (pps_i = '1' and pps_valid_i = '1') then
      tm_serial_o <= '1';
      state <= wt_utc;
      else
      tm_serial_o <= '0';
      end if;
      when wt_utc =>
      tm_serial_o <= '0';
      tm_utc_int <= tm_utc_i;
      cnt <= to_unsigned(40,6);
      state <= tx_utc;
      when tx_utc =>
      tm_serial_o <= tm_utc_int(tm_utc_int'high);
      tm_utc_int <= tm_utc_int(tm_utc_int'high-1 downto 0) & '0';
      if cnt = 0 then
      state <= idle;
      else
      cnt <= cnt -1;
      end if;
      when others => state <= idle;
      end case;
      end if;
      end if;
      end process p_tm_serial;
      end beha;
      \ No newline at end of file
      modules/wr_sma_config/xwr_sma_config.vhd 0 → 100644
      View file @ 50d6bf22
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      library work;
      use work.wishbone_pkg.all;
      use work.gencores_pkg.all;
      use work.sma_config_wbgen2_pkg.all;
      use work.sma_config_pkg.all;
      library UNISIM;
      use UNISIM.vcomponents.all;
      entity xwr_sma_config is
      generic (
      g_interface_mode : t_wishbone_interface_mode := PIPELINED;
      g_address_granularity : t_wishbone_address_granularity := WORD
      );
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      clk_serdes_i : in std_logic;
      pps_csync_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_tai_i : in std_logic_vector(39 downto 0);
      sync_data_o_p : out std_logic_vector(1 downto 0);
      sync_data_o_n : out std_logic_vector(1 downto 0);
      fdly_en_o : out std_logic;
      fdly_sload_o : out std_logic;
      fdly_sdin_o : out std_logic;
      fdly_sclk_o : out std_logic;
      slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
      slave_o : out t_wishbone_slave_out
      );
      attribute maxdelay : string;
      attribute maxdelay of pps_csync_i : signal is "1000 ps";
      end xwr_sma_config;
      architecture behav of xwr_sma_config is
      signal rst_sys_n : std_logic;
      signal rst_oserdes_pll : std_logic;
      signal pll_500m_locked : std_logic;
      signal clk_500m_fb : std_logic;
      signal clk_500m : std_logic;
      signal rst_oserdes : std_logic;
      signal sd_out0_p : std_logic_vector(0 downto 0);
      signal sd_out0_n : std_logic_vector(0 downto 0);
      signal sd_out1_p : std_logic_vector(0 downto 0);
      signal sd_out1_n : std_logic_vector(0 downto 0);
      signal customed_sd_data : std_logic_vector(c_DATA_W-1 downto 0);
      signal pps_sd_data : std_logic_vector(c_DATA_W-1 downto 0);
      signal utc_coding_sd_data : std_logic_vector(c_DATA_W-1 downto 0);
      signal ch0_sd_data : std_logic_vector(c_DATA_W-1 downto 0);
      signal ch1_sd_data : std_logic_vector(c_DATA_W-1 downto 0);
      signal wb_in : t_wishbone_slave_in;
      signal wb_out : t_wishbone_slave_out;
      signal ch0_sel : std_logic_vector(7 downto 0);
      signal ch1_sel : std_logic_vector(7 downto 0);
      signal cus_high_len: unsigned(28 downto 0);
      signal cus_low_len : unsigned(28 downto 0);
      signal cus_shift : unsigned(28 downto 0);
      signal cus_pps_valid_d : std_logic;
      signal cus_realign : std_logic;
      signal cus_new_freq : std_logic;
      signal utc_clk_shift : unsigned(25 downto 0);
      signal utc_phase_shift : unsigned(2 downto 0);
      signal utc_pps_valid_d : std_logic;
      signal utc_realign : std_logic;
      signal utc_new_freq : std_logic;
      signal utc_serial : std_logic;
      signal pps_clk_shift : unsigned(25 downto 0);
      signal pps_high_len : unsigned(25 downto 0);
      signal pps_phase_shift : unsigned(2 downto 0);
      signal pps_valid_d : std_logic;
      signal pps_realign : std_logic;
      signal pps_new_freq : std_logic;
      signal pps_serial : std_logic;
      signal wb_regs_in : t_sma_config_in_registers;
      signal wb_regs_out : t_sma_config_out_registers;
      signal fine_dly_req : std_logic;
      signal fine_dly_sel : std_logic;
      signal fine_dly_busy : std_logic;
      signal fine_dly_values : std_logic_vector(8 downto 0);
      signal sma0_fdly : std_logic_vector(8 downto 0);
      signal sma1_fdly : std_logic_vector(8 downto 0);
      signal fdly_en : std_logic;
      signal fdly_sload : std_logic;
      signal fdly_sdin : std_logic;
      signal fdly_sclk : std_logic;
      signal tm_utc_int : std_logic_vector(39 downto 0);
      function f_parallel_gen_1 (rest: integer; v_bit: std_logic) return std_logic_vector is
      variable result : std_logic_vector(7 downto 0);
      begin
      for i in 0 to 7 loop
      if(i<rest) then
      result(i) := v_bit;
      else
      result(i) := not v_bit;
      end if;
      end loop;
      return result;
      end function;
      function f_parallel_gen_2 (rest: integer; v_bit: std_logic; index: integer) return std_logic_vector is
      variable result : std_logic_vector(7 downto 0);
      begin
      result := (others => v_bit);
      for i in 0 to 7 loop
      if(i>rest-1 and i< index) then
      result(i) := not v_bit;
      end if;
      end loop;
      return result;
      end function;
      attribute KEEP : string;
      attribute KEEP of cus_low_len : signal is "TRUE";
      attribute KEEP of cus_high_len : signal is "TRUE";
      begin
      rst_oserdes_pll <= not rst_sys_n;
      U_Sync_reset_sysclk : gc_sync_ffs
      generic map (
      g_sync_edge => "positive")
      port map (
      clk_i => clk_sys_i,
      rst_n_i => '1',
      data_i => rst_n_i,
      synced_o => rst_sys_n);
      ----------------------------------------------------------------
      -- Wishbone Aapter --
      ----------------------------------------------------------------
      U_Adapter : wb_slave_adapter
      generic map (
      g_master_use_struct => true,
      g_master_mode => CLASSIC,
      g_master_granularity => WORD,
      g_slave_use_struct => true,
      g_slave_mode => g_interface_mode,
      g_slave_granularity => g_address_granularity
      )
      port map (
      clk_sys_i => clk_sys_i,
      rst_n_i => rst_sys_n,
      slave_i => slave_i,
      slave_o => slave_o,
      master_i => wb_out,
      master_o => wb_in
      );
      U_WB_IF: sma_config_wb
      port map (
      rst_n_i => rst_sys_n,
      clk_sys_i => clk_sys_i,
      wb_adr_i => wb_in.adr(3 downto 0),
      wb_dat_i => wb_in.dat,
      wb_dat_o => wb_out.dat,
      wb_cyc_i => wb_in.cyc,
      wb_sel_i => wb_in.sel,
      wb_stb_i => wb_in.stb,
      wb_we_i => wb_in.we,
      wb_ack_o => wb_out.ack,
      wb_stall_o=> wb_out.stall,
      regs_i => wb_regs_in,
      regs_o => wb_regs_out
      );
      wb_out.err <= '0';
      wb_out.rty <= '0';
      ----------------------------------------------------------------
      -- Fdly Controller --
      ----------------------------------------------------------------
      P_FDLY_CTRL: process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if(rst_sys_n = '0') then
      fine_dly_req <= '0';
      fine_dly_sel <= '0';
      else
      if(wb_regs_out.sma0_fdly_load_o = '1' and fine_dly_busy = '0') then
      fine_dly_req <= '1';
      fine_dly_sel <= '0';
      fine_dly_values <= wb_regs_out.sma0_fdly_o;
      elsif(wb_regs_out.sma1_fdly_load_o = '1' and fine_dly_busy = '0') then
      fine_dly_req <= '1';
      fine_dly_sel <= '1';
      fine_dly_values <= wb_regs_out.sma1_fdly_o;
      else
      fine_dly_req <= '0';
      fine_dly_values <= (others => '0');
      end if;
      end if;
      end if;
      end process;
      P_FDLY_RD: process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if(rst_sys_n = '0') then
      sma0_fdly <= (others => '0');
      sma1_fdly <= (others => '0');
      else
      if(fine_dly_req = '1') then
      if(fine_dly_sel = '0') then
      sma0_fdly <= fine_dly_values;
      else
      sma1_fdly <= fine_dly_values;
      end if;
      end if;
      end if;
      end if;
      end process;
      wb_regs_in.sma0_fdly_i <= sma0_fdly;
      wb_regs_in.sma1_fdly_i <= sma1_fdly;
      U_FDLY_CTRL: fine_delay_ctrl
      port map(
      rst_sys_n_i => rst_sys_n,
      clk_sys_i => clk_sys_i,
      fine_dly_req_i => fine_dly_req,
      fine_dly_sel_i => fine_dly_sel,
      fine_dly_values_i => fine_dly_values,
      fine_dly_busy_o => fine_dly_busy,
      delay_en_o => fdly_en,
      delay_sload_o => fdly_sload,
      delay_sdin_o => fdly_sdin,
      delay_sclk_o => fdly_sclk
      );
      fdly_en_o <= fdly_en;
      fdly_sload_o <= fdly_sload;
      fdly_sdin_o <= fdly_sdin;
      fdly_sclk_o <= fdly_sclk;
      ----------------------------------------------------------------
      -- Customed Generator --
      ----------------------------------------------------------------
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      -- if cus_new_freq or pll lost lock,
      -- force alignment to next PPS
      if(rst_sys_n = '0' or cus_new_freq = '1') then
      cus_pps_valid_d <= '0';
      elsif(pps_csync_i = '1') then
      cus_pps_valid_d <= pps_valid_i;
      end if;
      end if;
      end process;
      cus_realign <= (not cus_pps_valid_d) and pps_valid_i and pps_csync_i;
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      cus_high_len <= to_unsigned(c_HALF, cus_high_len'length);
      cus_low_len <= to_unsigned(c_HALF, cus_low_len'length);
      cus_shift <= to_unsigned(0, cus_shift'length);
      cus_new_freq <= '0';
      elsif wb_regs_out.cus_prh_load_o = '1' then
      cus_high_len <= unsigned(wb_regs_out.cus_prh_o);
      cus_new_freq <= '1';
      elsif wb_regs_out.cus_prl_load_o = '1' then
      cus_low_len <= unsigned(wb_regs_out.cus_prl_o);
      cus_new_freq <= '1';
      elsif wb_regs_out.cus_csr_load_o = '1' then
      cus_shift <= unsigned(wb_regs_out.cus_csr_o);
      cus_new_freq <= '1';
      else
      cus_new_freq <= '0';
      end if;
      end if;
      end process;
      wb_regs_in.cus_prh_i <= std_logic_vector(cus_high_len);
      wb_regs_in.cus_prl_i <= std_logic_vector(cus_low_len);
      wb_regs_in.cus_csr_i <= std_logic_vector(cus_shift);
      process(clk_sys_i)
      variable rest : integer range 0 to 536870911;
      variable rest_d : integer range 0 to 536870911;
      variable v_bit : std_logic;
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n='0' or cus_realign='1') then
      rest := to_integer(cus_shift);
      rest_d := rest + to_integer(cus_high_len);
      customed_sd_data <= (others => '0');
      v_bit := '0';
      else
      if(rest > 7) then
      customed_sd_data <= (others => v_bit);
      rest := rest - 8;
      else
      if(rest_d > 7) then
      customed_sd_data <= f_parallel_gen_1(rest,v_bit);
      rest := rest_d-8;
      v_bit := not v_bit;
      else
      customed_sd_data <= f_parallel_gen_2(rest,v_bit,rest_d);
      if(v_bit = '1')then
      rest := rest_d+to_integer(cus_high_len)-8;
      else
      rest := rest_d+to_integer(cus_low_len)-8;
      end if;
      end if;
      end if;
      if(v_bit = '1')then
      rest_d := rest + to_integer(cus_low_len);
      else
      rest_d := rest + to_integer(cus_high_len);
      end if;
      --for i in 0 to c_DATA_W-1 loop
      -- if(rest /= 0) then
      -- customed_sd_data(i) <= v_bit;
      -- rest := rest - 1;
      -- elsif(v_bit = '1') then
      -- customed_sd_data(i) <= '0';
      -- v_bit := '0';
      -- rest := to_integer(cus_low_len-1);
      -- elsif(v_bit = '0') then
      -- customed_sd_data(i) <= '1';
      -- v_bit := '1';
      -- rest := to_integer(cus_high_len-1);
      -- end if;
      --end loop;
      end if;
      end if;
      end process;
      ----------------------------------------------------------------
      -- UTC Coding --
      ----------------------------------------------------------------
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      -- if utc_new_freq or pll lost lock,
      -- force alignment to next PPS
      if(rst_sys_n = '0' or utc_new_freq = '1') then
      utc_pps_valid_d <= '0';
      elsif(pps_csync_i = '1') then
      utc_pps_valid_d <= pps_valid_i;
      end if;
      end if;
      end process;
      utc_realign <= (not utc_pps_valid_d) and pps_valid_i and pps_csync_i;
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      utc_clk_shift <= to_unsigned(0, utc_clk_shift'length);
      utc_phase_shift <= to_unsigned(0, utc_phase_shift'length);
      utc_new_freq <= '0';
      elsif wb_regs_out.utc_csr_load_o = '1' then
      utc_clk_shift <= unsigned(wb_regs_out.utc_csr_o(28 downto 3));
      utc_phase_shift <= unsigned(wb_regs_out.utc_csr_o(2 downto 0));
      utc_new_freq <= '1';
      else
      utc_new_freq <= '0';
      end if;
      end if;
      end process;
      wb_regs_in.utc_csr_i(28 downto 3) <= std_logic_vector(utc_clk_shift);
      wb_regs_in.utc_csr_i(2 downto 0) <= std_logic_vector(utc_phase_shift);
      process(clk_sys_i)
      type utc_state is (wait_pps, idle, wt_utc, tx_utc);
      variable state_u : utc_state;
      variable clk_rest : integer range 0 to 62499999;
      variable phase_rest : integer range 0 to 7;
      variable cnt : integer range 0 to 40;
      variable v_bit : std_logic;
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n='0' or utc_realign='1') then
      clk_rest := to_integer(utc_clk_shift);
      phase_rest := to_integer(utc_phase_shift);
      cnt := 0;
      state_u := wait_pps;
      v_bit := '0';
      utc_serial <= '0';
      tm_utc_int <= (others => '0');
      utc_coding_sd_data <= (others => '0');
      else
      case state_u is
      when wait_pps =>
      utc_serial <= '0';
      if (pps_csync_i = '1' and pps_valid_i = '1') then
      tm_utc_int <= tm_tai_i;
      if(utc_clk_shift = 0)then
      clk_rest := 0;
      state_u := wt_utc;
      utc_serial <= '1';
      else
      clk_rest := to_integer(utc_clk_shift) - 1;
      state_u := idle;
      utc_serial <= '0';
      end if;
      phase_rest := to_integer(utc_phase_shift);
      end if;
      when idle =>
      if (clk_rest /= 0)then
      clk_rest := clk_rest - 1;
      utc_serial <= '0';
      else
      state_u := wt_utc;
      utc_serial <= '1';
      end if;
      when wt_utc =>
      utc_serial <= '0';
      cnt := 40;
      state_u := tx_utc;
      when tx_utc =>
      utc_serial <= tm_utc_int(tm_utc_int'high);
      tm_utc_int <= tm_utc_int(tm_utc_int'high-1 downto 0) & '0';
      if cnt = 0 then
      state_u := wait_pps;
      else
      cnt := cnt -1;
      end if;
      when others => state_u := wait_pps;
      end case;
      for i in 0 to c_DATA_W-1 loop
      if(i < phase_rest) then
      utc_coding_sd_data(i) <= v_bit;
      else
      utc_coding_sd_data(i) <= utc_serial;
      v_bit := utc_serial;
      end if;
      end loop;
      end if;
      end if;
      end process;
      ----------------------------------------------------------------
      -- PPS --
      ----------------------------------------------------------------
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      -- if pps_new_freq or pll lost lock,
      -- force alignment to next PPS
      if(rst_sys_n = '0' or pps_new_freq = '1') then
      pps_valid_d <= '0';
      elsif(pps_csync_i = '1') then
      pps_valid_d <= pps_valid_i;
      end if;
      end if;
      end process;
      pps_realign <= (not pps_valid_d) and pps_valid_i and pps_csync_i;
      process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      pps_clk_shift <= to_unsigned(0, pps_clk_shift'length);
      pps_phase_shift <= to_unsigned(0, pps_phase_shift'length);
      pps_high_len <= to_unsigned(8, pps_high_len'length);
      pps_new_freq <= '0';
      elsif wb_regs_out.pps_csr_load_o = '1' then
      pps_clk_shift <= unsigned(wb_regs_out.pps_csr_o(28 downto 3));
      pps_phase_shift <= unsigned(wb_regs_out.pps_csr_o(2 downto 0));
      pps_new_freq <= '1';
      elsif wb_regs_out.pps_prh_load_o = '1' then
      pps_high_len <= unsigned(wb_regs_out.pps_prh_o(25 downto 0));
      pps_new_freq <= '1';
      else
      pps_new_freq <= '0';
      end if;
      end if;
      end process;
      wb_regs_in.pps_csr_i(28 downto 3) <= std_logic_vector(pps_clk_shift);
      wb_regs_in.pps_csr_i(2 downto 0) <= std_logic_vector(pps_phase_shift);
      wb_regs_in.pps_prh_i(25 downto 0) <= std_logic_vector(pps_high_len);
      process(clk_sys_i)
      type pps_state is (wait_pps, cdelay, last);
      variable state_p : pps_state;
      variable clk_rest : integer range 0 to 62499999;
      variable phase_rest : integer range 0 to 7;
      variable v_bit : std_logic;
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n='0' or pps_realign='1') then
      clk_rest := to_integer(pps_clk_shift);
      phase_rest := to_integer(pps_phase_shift);
      state_p := wait_pps;
      v_bit := '0';
      pps_serial <= '0';
      pps_sd_data <= (others => '0');
      else
      case state_p is
      when wait_pps =>
      pps_serial <= '0';
      if (pps_csync_i = '1') then
      if(pps_clk_shift = 0)then
      clk_rest := to_integer(pps_high_len)-1;
      state_p := last;
      pps_serial <= '1';
      else
      clk_rest := to_integer(pps_clk_shift) - 1;
      state_p := cdelay;
      pps_serial <= '0';
      end if;
      phase_rest := to_integer(pps_phase_shift);
      end if;
      when cdelay =>
      if (clk_rest /= 0)then
      clk_rest := clk_rest - 1;
      pps_serial <= '0';
      else
      clk_rest := to_integer(pps_high_len)-1;
      state_p := last;
      pps_serial <= '1';
      end if;
      when last =>
      if (clk_rest /= 0)then
      clk_rest := clk_rest - 1;
      pps_serial <= '1';
      else
      pps_serial <= '0';
      state_p := wait_pps;
      end if;
      when others => state_p := wait_pps;
      end case;
      for i in 0 to c_DATA_W-1 loop
      if(i < phase_rest) then
      pps_sd_data(i) <= v_bit;
      else
      pps_sd_data(i) <= pps_serial;
      v_bit := pps_serial;
      end if;
      end loop;
      end if;
      end if;
      end process;
      ----------------------------------------------------------------
      -- Serdes --
      ----------------------------------------------------------------
      P_LOAD_CFG: process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      ch0_sel <= (others => '0');
      ch1_sel <= (others => '0');
      elsif wb_regs_out.sma0_mux_load_o = '1' then
      ch0_sel <= wb_regs_out.sma0_mux_o;
      elsif wb_regs_out.sma1_mux_load_o= '1' then
      ch1_sel <= wb_regs_out.sma1_mux_o;
      end if;
      end if;
      end process;
      wb_regs_in.sma0_mux_i <= ch0_sel;
      wb_regs_in.sma1_mux_i <= ch1_sel;
      P_CH0_MUX: process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      ch0_sd_data <= "00000000";
      else
      case ch0_sel is
      when "00000000" =>
      ch0_sd_data <= pps_sd_data;
      when "00000001" =>
      ch0_sd_data <= utc_coding_sd_data;
      when "00000010" =>
      ch0_sd_data <= customed_sd_data;
      when others =>
      ch0_sd_data <= (others => '0');
      end case;
      end if;
      end if;
      end process;
      P_utc_MUX: process(clk_sys_i)
      begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n = '0') then
      ch1_sd_data <= "00000000";
      else
      case ch1_sel is
      when "00000000" =>
      ch1_sd_data <= pps_sd_data;
      when "00000001" =>
      ch1_sd_data <= utc_coding_sd_data;
      when "00000010" =>
      ch1_sd_data <= customed_sd_data;
      when others =>
      ch1_sd_data <= (others => '0');
      end case;
      end if;
      end if;
      end process;
      cmp_oserdes_clk_pll : MMCME2_ADV
      generic map (
      BANDWIDTH => "OPTIMIZED",
      CLKOUT4_CASCADE => false,
      COMPENSATION => "ZHOLD",
      STARTUP_WAIT => false,
      DIVCLK_DIVIDE => 1,
      CLKFBOUT_MULT_F => 8.000, -- 125 MHz -> 1 GHz
      CLKFBOUT_PHASE => 0.000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKOUT0_DIVIDE_F => 2.000, -- 1GHz/2 -> 500 MHz
      CLKOUT0_PHASE => 0.000,
      CLKOUT0_DUTY_CYCLE => 0.500,
      CLKOUT0_USE_FINE_PS => false,
      CLKOUT1_DIVIDE => 2, -- 1GHz/2 -> 500 MHz
      CLKOUT1_PHASE => 0.000,
      CLKOUT1_DUTY_CYCLE => 0.500,
      CLKOUT1_USE_FINE_PS => false,
      CLKIN1_PERIOD => 8.000, -- 8ns for 125 MHz
      REF_JITTER1 => 0.010)
      port map (
      -- Output clocks
      CLKFBOUT => clk_500m_fb,
      CLKOUT0 => clk_500m,
      -- Input clock control
      CLKFBIN => clk_500m_fb,
      CLKIN1 => clk_serdes_i,
      CLKIN2 => '0',
      -- Tied to always select the primary input clock
      CLKINSEL => '1',
      -- Ports for dynamic reconfiguration
      DADDR => (others => '0'),
      DCLK => '0',
      DEN => '0',
      DI => (others => '0'),
      DO => open,
      DRDY => open,
      DWE => '0',
      -- Ports for dynamic phase shift
      PSCLK => '0',
      PSEN => '0',
      PSINCDEC => '0',
      PSDONE => open,
      -- Other control and status signals
      LOCKED => pll_500m_locked,
      CLKINSTOPPED => open,
      CLKFBSTOPPED => open,
      PWRDWN => '0',
      RST => rst_oserdes_pll);
      rst_oserdes <= not pll_500m_locked;
      U_10MHZ_SERDES: oserdes_8_to_1
      generic map(
      dev_w => c_DATA_W)
      port map(
      DATA_OUT_FROM_DEVICE => ch0_sd_data,
      DATA_OUT_TO_PINS_P => sd_out0_p,
      DATA_OUT_TO_PINS_N => sd_out0_n,
      CLK_IN => clk_500m,
      CLK_DIV_IN => clk_sys_i,
      IO_RESET => rst_oserdes
      );
      sync_data_o_p(0) <= sd_out0_p(0);
      sync_data_o_n(0) <= sd_out0_n(0);
      U_PPS_SERDES: oserdes_8_to_1
      generic map(
      dev_w => c_DATA_W)
      port map(
      DATA_OUT_FROM_DEVICE => ch1_sd_data,
      DATA_OUT_TO_PINS_P => sd_out1_p,
      DATA_OUT_TO_PINS_N => sd_out1_n,
      CLK_IN => clk_500m,
      CLK_DIV_IN => clk_sys_i,
      IO_RESET => rst_oserdes
      );
      sync_data_o_p(1) <= sd_out1_p(0);
      sync_data_o_n(1) <= sd_out1_n(0);
      end behav;
      modules/wrc_core/wr_core.vhd
      View file @ 50d6bf22
      ......@@ -108,6 +108,7 @@ entity wr_core is
      g_diag_ro_size : integer := 0;
      g_diag_rw_size : integer := 0;
      g_num_phys : integer := 2;
      g_muxed_ports : integer := 3;
      g_num_softpll_inputs : integer := 2;
      g_with_10M_output : boolean := true
      );
      ......@@ -139,6 +140,10 @@ entity wr_core is
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      ......@@ -342,11 +347,12 @@ entity wr_core is
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      -- clk output
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -551,11 +557,11 @@ architecture struct of wr_core is
      signal ep_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal ep_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0);
      signal mux_src_out : t_wrf_source_out_array(3*g_num_phys-1 downto 0);
      signal mux_src_in : t_wrf_source_in_array(3*g_num_phys-1 downto 0);
      signal mux_snk_out : t_wrf_sink_out_array(3*g_num_phys-1 downto 0);
      signal mux_snk_in : t_wrf_sink_in_array(3*g_num_phys-1 downto 0);
      signal mux_class : t_wrf_mux_class(2 downto 0);
      signal mux_src_out : t_wrf_source_out_array(g_muxed_ports*g_num_phys-1 downto 0);
      signal mux_src_in : t_wrf_source_in_array(g_muxed_ports*g_num_phys-1 downto 0);
      signal mux_snk_out : t_wrf_sink_out_array(g_muxed_ports*g_num_phys-1 downto 0);
      signal mux_snk_in : t_wrf_sink_in_array(g_muxed_ports*g_num_phys-1 downto 0);
      signal mux_class : t_wrf_mux_class(g_muxed_ports-1 downto 0);
      signal spll_out_locked : std_logic_vector(g_aux_clks downto 0);
      ......@@ -673,15 +679,24 @@ begin
      slave_o => ppsg_wb_out,
      -- used for fast masking of PPS output when link goes down
      link_ok_i => ppsg_link_ok,
      --link_ok_i => ppsg_link_ok,
      -- keep PPS generation
      link_ok_i => '1',
      -- Single-pulse PPS output for synchronizing endpoint to
      pps_in_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      pps_csync_o => s_pps_csync,
      pps_valid_int_o => pps_valid,
      pps_out_o => pps_p_o,
      pps_led_o => pps_led_o,
      pps_valid_o => pps_valid,
      pps_valid_o => pps_valid_o,
      pps_unmask_o => pps_unmask_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      tm_utc_o => tm_tai_o,
      tm_cycles_o => tm_cycles_o,
      ......@@ -689,7 +704,7 @@ begin
      );
      ppsg_link_ok <= not phy_rst(0);
      pps_csync_o <= s_pps_csync;
      pps_valid_o <= pps_valid;
      -----------------------------------------------------------------------------
      -- Software PLL
      ......@@ -966,10 +981,10 @@ begin
      clk_sys_i => clk_sys_i,
      rst_n_i => rst_net_n,
      src_o => mux_snk_in(3*i),
      src_i => mux_snk_out(3*i),
      snk_o => mux_src_in(3*i),
      snk_i => mux_src_out(3*i),
      src_o => mux_snk_in(g_muxed_ports*i),
      src_i => mux_snk_out(g_muxed_ports*i),
      snk_o => mux_src_in(g_muxed_ports*i),
      snk_i => mux_src_out(g_muxed_ports*i),
      txtsu_port_id_i => ep_txtsu_port_id((i+1)*5-1 downto i*5),
      txtsu_frame_id_i => ep_txtsu_frame_id((i+1)*16-1 downto i*16),
      ......@@ -1131,8 +1146,8 @@ begin
      rst_n_i => rst_n_i,
      pps_i => s_pps_csync,
      pps_valid_i => pps_valid,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      sync_clk_10m_o_p => sync_clk_10m_o_p,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      slave_i => secbar_master_o(10),
      slave_o => secbar_master_i(10));
      ......@@ -1272,7 +1287,7 @@ begin
      U_WBP_Mux : xwrf_mux
      generic map(
      g_muxed_ports => 3)
      g_muxed_ports => g_muxed_ports)
      port map (
      clk_sys_i => clk_sys_i,
      rst_n_i => rst_net_n,
      ......@@ -1280,61 +1295,61 @@ begin
      ep_src_i => ep_snk_out(i),
      ep_snk_o => ep_src_in(i),
      ep_snk_i => ep_src_out(i),
      mux_src_o => mux_src_out((i+1)*3-1 downto i*3),
      mux_src_i => mux_src_in((i+1)*3-1 downto i*3),
      mux_snk_o => mux_snk_out((i+1)*3-1 downto i*3),
      mux_snk_i => mux_snk_in((i+1)*3-1 downto i*3),
      mux_src_o => mux_src_out((i+1)*g_muxed_ports-1 downto i*g_muxed_ports),
      mux_src_i => mux_src_in((i+1)*g_muxed_ports-1 downto i*g_muxed_ports),
      mux_snk_o => mux_snk_out((i+1)*g_muxed_ports-1 downto i*g_muxed_ports),
      mux_snk_i => mux_snk_in((i+1)*g_muxed_ports-1 downto i*g_muxed_ports),
      mux_class_i => mux_class);
      wrf_src_o(i).adr <= mux_src_out((i+1)*3-1).adr;
      wrf_src_o(i).dat <= mux_src_out((i+1)*3-1).dat;
      wrf_src_o(i).stb <= mux_src_out((i+1)*3-1).stb;
      wrf_src_o(i).cyc <= mux_src_out((i+1)*3-1).cyc;
      wrf_src_o(i).sel <= mux_src_out((i+1)*3-1).sel;
      wrf_src_o(i).adr <= mux_src_out((i+1)*g_muxed_ports-1).adr;
      wrf_src_o(i).dat <= mux_src_out((i+1)*g_muxed_ports-1).dat;
      wrf_src_o(i).stb <= mux_src_out((i+1)*g_muxed_ports-1).stb;
      wrf_src_o(i).cyc <= mux_src_out((i+1)*g_muxed_ports-1).cyc;
      wrf_src_o(i).sel <= mux_src_out((i+1)*g_muxed_ports-1).sel;
      wrf_src_o(i).we <= '1';
      mux_src_in((i+1)*3-1).ack <= wrf_src_i(i).ack;
      mux_src_in((i+1)*3-1).stall <= wrf_src_i(i).stall;
      mux_src_in((i+1)*3-1).err <= wrf_src_i(i).err;
      mux_src_in((i+1)*3-1).rty <= '0';
      mux_src_in((i+1)*g_muxed_ports-1).ack <= wrf_src_i(i).ack;
      mux_src_in((i+1)*g_muxed_ports-1).stall <= wrf_src_i(i).stall;
      mux_src_in((i+1)*g_muxed_ports-1).err <= wrf_src_i(i).err;
      mux_src_in((i+1)*g_muxed_ports-1).rty <= '0';
      mux_snk_in((i+1)*3-1).adr <= wrf_snk_i(i).adr;
      mux_snk_in((i+1)*3-1).dat <= wrf_snk_i(i).dat;
      mux_snk_in((i+1)*3-1).stb <= wrf_snk_i(i).stb;
      mux_snk_in((i+1)*3-1).cyc <= wrf_snk_i(i).cyc;
      mux_snk_in((i+1)*3-1).sel <= wrf_snk_i(i).sel;
      mux_snk_in((i+1)*3-1).we <= wrf_snk_i(i).we;
      wrf_snk_o(i).ack <= mux_snk_out((i+1)*3-1).ack;
      wrf_snk_o(i).err <= mux_snk_out((i+1)*3-1).err;
      wrf_snk_o(i).stall <= mux_snk_out((i+1)*3-1).stall;
      mux_snk_in((i+1)*g_muxed_ports-1).adr <= wrf_snk_i(i).adr;
      mux_snk_in((i+1)*g_muxed_ports-1).dat <= wrf_snk_i(i).dat;
      mux_snk_in((i+1)*g_muxed_ports-1).stb <= wrf_snk_i(i).stb;
      mux_snk_in((i+1)*g_muxed_ports-1).cyc <= wrf_snk_i(i).cyc;
      mux_snk_in((i+1)*g_muxed_ports-1).sel <= wrf_snk_i(i).sel;
      mux_snk_in((i+1)*g_muxed_ports-1).we <= wrf_snk_i(i).we;
      wrf_snk_o(i).ack <= mux_snk_out((i+1)*g_muxed_ports-1).ack;
      wrf_snk_o(i).err <= mux_snk_out((i+1)*g_muxed_ports-1).err;
      wrf_snk_o(i).stall <= mux_snk_out((i+1)*g_muxed_ports-1).stall;
      wrf_snk_o(i).rty <= '0';
      eb_wrf_src_o(i).adr <= mux_src_out((i+1)*3-2).adr;
      eb_wrf_src_o(i).dat <= mux_src_out((i+1)*3-2).dat;
      eb_wrf_src_o(i).stb <= mux_src_out((i+1)*3-2).stb;
      eb_wrf_src_o(i).cyc <= mux_src_out((i+1)*3-2).cyc;
      eb_wrf_src_o(i).sel <= mux_src_out((i+1)*3-2).sel;
      eb_wrf_src_o(i).adr <= mux_src_out((i+1)*g_muxed_ports-2).adr;
      eb_wrf_src_o(i).dat <= mux_src_out((i+1)*g_muxed_ports-2).dat;
      eb_wrf_src_o(i).stb <= mux_src_out((i+1)*g_muxed_ports-2).stb;
      eb_wrf_src_o(i).cyc <= mux_src_out((i+1)*g_muxed_ports-2).cyc;
      eb_wrf_src_o(i).sel <= mux_src_out((i+1)*g_muxed_ports-2).sel;
      eb_wrf_src_o(i).we <= '1';
      mux_src_in((i+1)*3-2).ack <= eb_wrf_src_i(i).ack;
      mux_src_in((i+1)*3-2).stall <= eb_wrf_src_i(i).stall;
      mux_src_in((i+1)*3-2).err <= eb_wrf_src_i(i).err;
      mux_src_in((i+1)*3-2).rty <= '0';
      mux_src_in((i+1)*g_muxed_ports-2).ack <= eb_wrf_src_i(i).ack;
      mux_src_in((i+1)*g_muxed_ports-2).stall <= eb_wrf_src_i(i).stall;
      mux_src_in((i+1)*g_muxed_ports-2).err <= eb_wrf_src_i(i).err;
      mux_src_in((i+1)*g_muxed_ports-2).rty <= '0';
      mux_snk_in((i+1)*3-2).adr <= eb_wrf_snk_i(i).adr;
      mux_snk_in((i+1)*3-2).dat <= eb_wrf_snk_i(i).dat;
      mux_snk_in((i+1)*3-2).stb <= eb_wrf_snk_i(i).stb;
      mux_snk_in((i+1)*3-2).cyc <= eb_wrf_snk_i(i).cyc;
      mux_snk_in((i+1)*3-2).sel <= eb_wrf_snk_i(i).sel;
      mux_snk_in((i+1)*3-2).we <= eb_wrf_snk_i(i).we;
      eb_wrf_snk_o(i).ack <= mux_snk_out((i+1)*3-2).ack;
      eb_wrf_snk_o(i).err <= mux_snk_out((i+1)*3-2).err;
      eb_wrf_snk_o(i).stall <= mux_snk_out((i+1)*3-2).stall;
      mux_snk_in((i+1)*g_muxed_ports-2).adr <= eb_wrf_snk_i(i).adr;
      mux_snk_in((i+1)*g_muxed_ports-2).dat <= eb_wrf_snk_i(i).dat;
      mux_snk_in((i+1)*g_muxed_ports-2).stb <= eb_wrf_snk_i(i).stb;
      mux_snk_in((i+1)*g_muxed_ports-2).cyc <= eb_wrf_snk_i(i).cyc;
      mux_snk_in((i+1)*g_muxed_ports-2).sel <= eb_wrf_snk_i(i).sel;
      mux_snk_in((i+1)*g_muxed_ports-2).we <= eb_wrf_snk_i(i).we;
      eb_wrf_snk_o(i).ack <= mux_snk_out((i+1)*g_muxed_ports-2).ack;
      eb_wrf_snk_o(i).err <= mux_snk_out((i+1)*g_muxed_ports-2).err;
      eb_wrf_snk_o(i).stall <= mux_snk_out((i+1)*g_muxed_ports-2).stall;
      eb_wrf_snk_o(i).rty <= '0';
      end generate gen_WBP_MUX;
      mux_class(0) <= x"0f"; -- to lm32
      mux_class(1) <= x"10"; -- to etherbone
      mux_class(2) <= x"e0"; -- other external module
      mux_class(1) <= x"30"; -- to eb_wrf, other local module
      mux_class(2) <= x"c0"; -- to wrf, to another port
      -----------------------------------------------------------------------------
      -- External Tx Timestamping I/F
      ......
      modules/wrc_core/wrc_periph.vhd
      View file @ 50d6bf22
      ......@@ -509,6 +509,9 @@ begin
      generic map(
      g_with_virtual_uart => g_virtual_uart,
      g_with_physical_uart => g_phys_uart,
      g_with_physical_uart_fifo => true,
      g_tx_fifo_size => 256,
      g_rx_fifo_size => 256,
      g_interface_mode => PIPELINED,
      g_address_granularity => BYTE,
      g_vuart_fifo_size => g_vuart_fifo_size
      ......@@ -525,7 +528,6 @@ begin
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o
      );
      --------------------------------------
      -- 1-WIRE
      --------------------------------------
      ......
      modules/wrc_core/wrcore_pkg.vhd
      View file @ 50d6bf22
      ......@@ -86,9 +86,15 @@ package wrcore_pkg is
      pps_in_i : in std_logic;
      ppsin_term_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      tm_time_valid_o : out std_logic
      ......@@ -406,6 +412,10 @@ package wrcore_pkg is
      clk_ext_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      dac_hpll_load_p1_o : out std_logic;
      ......@@ -521,10 +531,11 @@ package wrcore_pkg is
      tm_cycles_o : out std_logic_vector(27 downto 0);
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -602,6 +613,10 @@ package wrcore_pkg is
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      -----------------------------------------
      ......@@ -800,10 +815,11 @@ package wrcore_pkg is
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -860,8 +876,8 @@ package wrcore_pkg is
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- can be wired to IODelay component in top module for precise 1-PPS
      -- alignment with clk_aux
      ......
      modules/wrc_core/xwr_core.vhd
      View file @ 50d6bf22
      ......@@ -136,6 +136,10 @@ entity xwr_core is
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      ......@@ -299,10 +303,11 @@ entity xwr_core is
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -365,6 +370,10 @@ begin
      clk_ext_rst_o => clk_ext_rst_o,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      rst_n_i => rst_n_i,
      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
      ......@@ -506,10 +515,11 @@ begin
      tm_cycles_o => tm_cycles_o,
      pps_csync_o => pps_csync_o,
      pps_valid_o => pps_valid_o,
      pps_unmask_o => pps_unmask_o,
      pps_p_o => pps_p_o,
      pps_led_o => pps_led_o,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      sync_clk_10m_o_p => sync_clk_10m_o_p,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      rst_aux_n_o => rst_aux_n_o,
      link_ok_o => link_ok_o,
      aux_diag_i => aux_diag_i,
      ......
      platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
      View file @ 50d6bf22
      ......@@ -108,9 +108,11 @@ architecture structure of wr_gtp_phy_family7 is
      type state_type_array is array(integer range <>) of state_type;
      signal state : state_type_array(g_num_phys-1 downto 0);
      signal rst_synced : std_logic_vector(1 downto 0);
      signal rst_int : std_logic_vector(1 downto 0);
      signal areset : std_logic_vector(g_num_phys-1 downto 0);
      signal rst_synced : std_logic_vector(g_num_phys-1 downto 0);
      signal rst_int : std_logic_vector(g_num_phys-1 downto 0);
      signal gttxreset : std_logic_vector(g_num_phys-1 downto 0);
      signal PLL_RESET : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_tx_buf : std_logic_vector(g_num_phys-1 downto 0);
      signal pll_locked : std_logic_vector(g_num_phys-1 downto 0);
      ......@@ -221,11 +223,12 @@ begin
      gen_RESET: for i in 0 to (g_num_phys-1) generate
      areset(i) <= areset_i or phy16_i(i).rst;
      -- PLL reset
      U_EdgeDet_areset_i : gc_sync_ffs port map (
      clk_i => clk_ref_i(i),
      rst_n_i => '1',
      data_i => areset_i,
      data_i => areset(i),
      ppulse_o => rst_synced(i));
      process(clk_ref_i(i), rst_synced(i))
      ......@@ -348,6 +351,10 @@ gen_GTP: for i in 0 to (g_num_phys-1) generate
      I => GT_CHANNEL_SIG_o(i).TXOUTCLK,
      O => clk_tx_buf(i));
      -- LPDC signals
      gttxreset(i) <= pll_locked_n(i) or phy16_i(i).lpc_ctrl(0);
      phy16_o(i).lpc_stat(0) <= GT_CHANNEL_SIG_o(i).TXRESETDONE;
      GT_CHANNEL_SIG_i(i).RST_IN <= '1' when state(i) = count_done else '0';
      GT_CHANNEL_SIG_i(i).DRPCLK_IN <= clk_ref_i(i);
      GT_CHANNEL_SIG_i(i).DRPDI_IN <= (others => '0');
      ......@@ -363,7 +370,7 @@ gen_GTP: for i in 0 to (g_num_phys-1) generate
      GT_CHANNEL_SIG_i(i).RXLPMHFHOLD <= '0';
      GT_CHANNEL_SIG_i(i).RXLPMLFHOLD <= '0';
      GT_CHANNEL_SIG_i(i).GTRXRESET <= gs(i).GTRXRESET;
      GT_CHANNEL_SIG_i(i).GTTXRESET <= pll_locked_n(i);
      GT_CHANNEL_SIG_i(i).GTTXRESET <= gttxreset(i);
      GT_CHANNEL_SIG_i(i).TXUSERRDY <= pll_locked(i);
      GT_CHANNEL_SIG_i(i).TXDATA(15 downto 0) <= phy16_i(i).tx_data(7 downto 0) & phy16_i(i).tx_data(15 downto 8);
      GT_CHANNEL_SIG_i(i).TXUSRCLK <= clk_tx_buf(i);
      ......
      platform/xilinx/xwrc_platform_xilinx.vhd
      View file @ 50d6bf22
      ......@@ -193,6 +193,8 @@ architecture rtl of xwrc_platform_xilinx is
      signal phy16_out : t_phy_16bits_to_wrc_array(2-1 downto 0);
      signal phy16_in : t_phy_16bits_from_wrc_array(2-1 downto 0):=(others=>c_dummy_phy16_from_wrc);
      signal clk_sys : std_logic;
      signal clk_sys_out : std_logic;
      signal pll_sys_locked : std_logic;
      begin -- architecture rtl
      ......@@ -217,7 +219,8 @@ begin -- architecture rtl
      -----------------------------------------------------------------------------
      -- active high async reset for PLLs
      pll_arst <= not areset_n_i;
      pll_arst <= not areset_n_i;
      clk_sys_o <= clk_sys_out;
      gen_default_plls : if (g_use_default_plls = TRUE) generate
      ......@@ -233,9 +236,7 @@ begin -- architecture rtl
      gen_spartan6_default_plls : if (g_fpga_family = "spartan6") generate
      signal clk_20m : std_logic;
      signal clk_sys_out : std_logic;
      signal clk_sys_fb : std_logic;
      signal pll_sys_locked : std_logic;
      signal clk_dmtd : std_logic;
      signal clk_dmtd_fb : std_logic;
      signal pll_dmtd_locked : std_logic;
      ......@@ -332,11 +333,10 @@ begin -- architecture rtl
      I => clk_pllref_buf_int2);
      clk_20m_o <= clk_20m_vcxo_buf;
      clk_sys_o <= clk_sys_out;
      clk_ref_o(0) <= clk_pllref_buf;
      clk_ref_o <= (others=>clk_pllref_buf);
      clk_ref_locked_o <= (others=>'1');
      pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
      pll_aux_locked_o <= pll_sys_locked;
      clk_ref_locked_o <= (others=>'1');
      -- DMTD PLL
      cmp_dmtd_clk_pll : PLL_BASE
      ......@@ -377,7 +377,7 @@ begin -- architecture rtl
      signal clk_ext_fbi : std_logic;
      signal clk_ext_fbo : std_logic;
      signal clk_ext_buf : std_logic;
      signal clk_ext : std_logic;
      signal clk_ext_mul : std_logic;
      signal clk_ext_stat : std_logic_vector(7 downto 0);
      signal pll_ext_rst : std_logic;
      ......@@ -402,7 +402,7 @@ begin -- architecture rtl
      CLKFB => clk_ext_fbi,
      -- Output clocks
      CLK0 => clk_ext_fbo,
      CLKFX => clk_ext,
      CLKFX => clk_ext_mul,
      -- Ports for dynamic phase shift
      PSCLK => '0',
      PSEN => '0',
      ......@@ -435,7 +435,7 @@ begin -- architecture rtl
      cmp_clk_ext_buf_o : BUFG
      port map
      (O => clk_ext_mul_o,
      I => clk_ext);
      I => clk_ext_mul);
      cmp_extend_ext_reset : gc_extend_pulse
      generic map (
      ......@@ -455,9 +455,7 @@ begin -- architecture rtl
      ---------------------------------------------------------------------------
      gen_virtex5_default_plls : if (g_fpga_family = "virtex5") generate
      signal clk_sys_out : std_logic;
      signal clk_sys_fb : std_logic;
      signal pll_sys_locked : std_logic;
      signal clk_dmtd : std_logic;
      signal clk_dmtd_fb : std_logic;
      signal pll_dmtd_locked : std_logic;
      ......@@ -499,10 +497,9 @@ begin -- architecture rtl
      O => clk_sys_out,
      I => clk_sys);
      clk_sys_o <= clk_sys_out;
      clk_ref_o(0) <= clk_pllref_buf;
      pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
      clk_ref_o(0) <= clk_pllref_buf;
      clk_ref_locked_o <= (others=>'1');
      pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
      -- DMTD PLL
      cmp_dmtd_clk_pll : PLL_BASE
      ......@@ -545,9 +542,7 @@ begin -- architecture rtl
      ---------------------------------------------------------------------------
      gen_kintex7_artix7_default_plls : if (g_fpga_family = "kintex7" or g_fpga_family = "artix7") generate
      signal clk_sys_out : std_logic;
      signal clk_sys_fb : std_logic;
      signal pll_sys_locked : std_logic;
      signal clk_dmtd : std_logic;
      signal clk_dmtd_fb : std_logic;
      signal pll_dmtd_locked : std_logic;
      ......@@ -608,7 +603,6 @@ begin -- architecture rtl
      I => clk_sys,
      O => clk_sys_out);
      clk_sys_o <= clk_sys_out;
      pll_locked_o <= pll_dmtd_locked and pll_sys_locked;
      gen_kintex7_artix7_dmtd_pll : if (g_direct_dmtd = FALSE) generate
      ......@@ -696,119 +690,19 @@ begin -- architecture rtl
      O => clk_dmtd_o,
      I => clk_dmtd);
      -- External 10MHz reference PLL for Kintex7 and Artix7
      gen_kintex7_artix7_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
      signal clk_ext_fbi : std_logic;
      signal clk_ext_fbo : std_logic;
      signal clk_ext_buf : std_logic;
      signal clk_ext_mul : std_logic;
      signal pll_ext_rst : std_logic;
      begin
      mmcm_adv_inst : MMCME2_ADV
      generic map (
      BANDWIDTH => "OPTIMIZED",
      CLKOUT4_CASCADE => FALSE,
      COMPENSATION => "ZHOLD",
      STARTUP_WAIT => FALSE,
      DIVCLK_DIVIDE => 1,
      CLKFBOUT_MULT_F => 62.500,
      CLKFBOUT_PHASE => 0.000,
      CLKFBOUT_USE_FINE_PS => FALSE,
      CLKOUT0_DIVIDE_F => 10.000,
      CLKOUT0_PHASE => 0.000,
      CLKOUT0_DUTY_CYCLE => 0.500,
      CLKOUT0_USE_FINE_PS => FALSE,
      CLKIN1_PERIOD => 100.000,
      REF_JITTER1 => 0.005)
      port map (
      -- Output clocks
      CLKFBOUT => clk_ext_fbo,
      CLKOUT0 => clk_ext_mul,
      -- Input clock control
      CLKFBIN => clk_ext_fbi,
      CLKIN1 => clk_ext_buf,
      CLKIN2 => '0',
      -- Tied to always select the primary input clock
      CLKINSEL => '1',
      -- Ports for dynamic reconfiguration
      DADDR => (others => '0'),
      DCLK => '0',
      DEN => '0',
      DI => (others => '0'),
      DO => open,
      DRDY => open,
      DWE => '0',
      -- Ports for dynamic phase shift
      PSCLK => '0',
      PSEN => '0',
      PSINCDEC => '0',
      PSDONE => open, -- Other control and status signals
      LOCKED => clk_ext_mul_locked_o,
      CLKINSTOPPED => clk_ext_mul_stopped_o,
      CLKFBSTOPPED => open,
      PWRDWN => '0',
      RST => pll_ext_rst);
      -- External reference input buffer
      cmp_clk_ext_buf_i : BUFG
      port map (
      O => clk_ext_buf,
      I => clk_ext_i);
      clk_ext_o <= clk_ext_buf;
      -- External reference feedback buffer
      cmp_clk_ext_buf_fb : BUFG
      port map (
      O => clk_ext_fbi,
      I => clk_ext_fbo);
      -- External reference output buffer
      cmp_clk_ext_buf_o : BUFG
      port map (
      O => clk_ext_mul_o,
      I => clk_ext_mul);
      cmp_extend_ext_reset : gc_extend_pulse
      generic map (
      g_width => 1000)
      port map (
      clk_i => clk_sys_out,
      rst_n_i => pll_sys_locked,
      pulse_i => clk_ext_rst_i,
      extended_o => pll_ext_rst);
      end generate gen_kintex7_artix7_ext_ref_pll;
      end generate gen_kintex7_artix7_default_plls;
      ---------------------------------------------------------------------------
      gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
      clk_ext_o <= '0';
      clk_ext_mul_o <= '0';
      clk_ext_mul_locked_o <= '1';
      clk_ext_mul_stopped_o <= '1';
      end generate gen_no_ext_ref_pll;
      end generate gen_default_plls;
      -- If external PLLs are used, just copy clock inputs to outputs
      gen_custom_plls : if (g_use_default_plls = FALSE) generate
      clk_sys_o <= clk_sys_i;
      clk_sys_out <= clk_sys_i;
      clk_dmtd_o <= clk_dmtd_i;
      -- clk_ref_o(0) <= clk_ref_i;
      clk_pllref_buf <= clk_ref_i;
      pll_sys_locked <= clk_sys_locked_i;
      pll_locked_o <= clk_sys_locked_i and clk_dmtd_locked_i;
      clk_ref_locked_o <= (others=>clk_ref_locked_i);
      clk_ext_mul_o <= clk_ext_mul_i;
      clk_ext_mul_locked_o <= clk_ext_locked_i;
      clk_ext_mul_stopped_o <= clk_ext_stopped_i;
      end generate gen_custom_plls;
      ......@@ -821,7 +715,6 @@ begin -- architecture rtl
      gen_phy_spartan6 : if(g_fpga_family = "spartan6") generate
      signal clk_gtp_buf : std_logic;
      signal clk_gtp : std_logic_vector(2-1 downto 0);
      signal pad_txn_out : std_logic_vector(2-1 downto 0);
      ......@@ -831,16 +724,25 @@ begin -- architecture rtl
      begin
      cmp_ibufgds_gtp : IBUFGDS
      cmp_ibufgds_gtp0 : IBUFGDS
      generic map (
      DIFF_TERM => TRUE,
      IBUF_LOW_PWR => TRUE,
      IOSTANDARD => "DEFAULT")
      port map (
      O => clk_gtp_buf,
      O => clk_gtp(0),
      I => clk_gtp_ref0_p_i,
      IB => clk_gtp_ref0_n_i);
      cmp_ibufgds_gtp1 : IBUFGDS
      generic map (
      DIFF_TERM => TRUE,
      IBUF_LOW_PWR => TRUE,
      IOSTANDARD => "DEFAULT")
      port map (
      O => clk_gtp(1),
      I => clk_gtp_ref1_p_i,
      IB => clk_gtp_ref1_n_i);
      cmp_gtp : wr_gtp_phy_spartan6
      generic map (
      ......@@ -893,8 +795,6 @@ begin -- architecture rtl
      );
      gen_gtp_ch0 : if (g_gtp_enable_ch0 = 1 and g_gtp_enable_ch1 = 0) generate
      clk_gtp(0) <= clk_gtp_buf;
      clk_gtp(1) <= '0';
      phy8_in(0) <= phy8_i(0);
      phy8_o(0) <= phy8_out(0);
      phy8_out(0).ref_clk <= clk_pllref_buf;
      ......@@ -909,8 +809,6 @@ begin -- architecture rtl
      end generate gen_gtp_ch0;
      gen_gtp_ch1 : if (g_gtp_enable_ch0 = 0 and g_gtp_enable_ch1 = 1) generate
      clk_gtp(0) <= '0';
      clk_gtp(1) <= clk_gtp_buf;
      phy8_in(1) <= phy8_i(0);
      phy8_o(0) <= phy8_out(1);
      phy8_out(1).ref_clk <= clk_pllref_buf;
      ......@@ -925,8 +823,6 @@ begin -- architecture rtl
      end generate gen_gtp_ch1;
      gen_gtp_ch01 : if (g_gtp_enable_ch0 = 1 and g_gtp_enable_ch1 = 1) generate
      clk_gtp(0) <= clk_gtp_buf;
      clk_gtp(1) <= '0';
      phy8_in <= phy8_i;
      phy8_o <= phy8_out;
      phy8_out(0).ref_clk <= clk_pllref_buf;
      ......@@ -954,7 +850,6 @@ begin -- architecture rtl
      gen_phy_virtex5 : if(g_fpga_family = "virtex5") generate
      signal clk_gtp : std_logic_vector(2-1 downto 0);
      signal clk_gtp_buf : std_logic;
      signal pad_txp_out : std_logic_vector(g_num_phys-1 downto 0);
      signal pad_txn_out : std_logic_vector(g_num_phys-1 downto 0);
      ......@@ -963,16 +858,25 @@ begin -- architecture rtl
      begin
      cmp_ibufgds_gtp : IBUFGDS
      cmp_ibufgds_gtp0 : IBUFGDS
      generic map (
      DIFF_TERM => FALSE, -- ?: Tom's true, VXS: false
      IBUF_LOW_PWR => TRUE, -- ?: Tom's commented out, VXS: true
      IOSTANDARD => "DEFAULT") -- OK
      port map (
      O => clk_gtp_buf,
      O => clk_gtp(0),
      I => clk_gtp_ref0_p_i,
      IB => clk_gtp_ref0_n_i);
      cmp_ibufgds_gtp1 : IBUFGDS
      generic map (
      DIFF_TERM => FALSE, -- ?: Tom's true, VXS: false
      IBUF_LOW_PWR => TRUE, -- ?: Tom's commented out, VXS: true
      IOSTANDARD => "DEFAULT") -- OK
      port map (
      O => clk_gtp(1),
      I => clk_gtp_ref1_p_i,
      IB => clk_gtp_ref1_n_i);
      cmp_gtp : wr_gtp_phy_virtex5
      generic map (
      ......@@ -980,7 +884,7 @@ begin -- architecture rtl
      g_enable_ch0 => g_gtp_enable_ch0,
      g_enable_ch1 => g_gtp_enable_ch1)
      port map (
      gtp_clk_i => clk_gtp_buf,
      gtp_clk_i => clk_gtp(0),
      ch01_ref_clk_i => clk_pllref_buf,
      ch0_tx_data_i => phy8_in(0).tx_data,
      ch0_tx_k_i => phy8_in(0).tx_k(0),
      ......@@ -1043,8 +947,6 @@ begin -- architecture rtl
      end generate gen_gtp_ch1;
      gen_gtp_ch01 : if (g_gtp_enable_ch0 = 1 and g_gtp_enable_ch1 = 1) generate
      clk_gtp(0) <= clk_gtp_buf;
      clk_gtp(1) <= '0';
      phy8_in <= phy8_i;
      phy8_o <= phy8_out;
      phy8_out(0).ref_clk <= clk_pllref_buf;
      ......@@ -1252,4 +1154,26 @@ begin -- architecture rtl
      end generate gen_phy_artix7;
      gen_no_ext_ref_pll : if (g_with_external_clock_input = FALSE) generate
      clk_ext_o <= '0';
      clk_ext_mul_o <= '0';
      clk_ext_mul_locked_o <= '1';
      clk_ext_mul_stopped_o <= '1';
      end generate gen_no_ext_ref_pll;
      gen_with_ext_ref_pll : if (g_with_external_clock_input = TRUE) generate
      clk_ext_mul_locked_o <= clk_ext_locked_i;
      clk_ext_mul_stopped_o <= clk_ext_stopped_i;
      cmp_clk_ext_mul_buf : BUFG
      port map (
      I => clk_ext_mul_i,
      O => clk_ext_mul_o
      );
      cmp_clk_ext_buf : BUFG
      port map (
      I => clk_ext_i,
      O => clk_ext_o
      );
      end generate gen_with_ext_ref_pll;
      end architecture rtl;
      sim/pps_gen_regs.v
      View file @ 50d6bf22
      `define ADDR_PPSG_CR 5'h0
      `define ADDR_PPSG_CR 6'h0
      `define PPSG_CR_CNT_RST_OFFSET 0
      `define PPSG_CR_CNT_RST 32'h00000001
      `define PPSG_CR_CNT_EN_OFFSET 1
      ......@@ -9,13 +9,13 @@
      `define PPSG_CR_CNT_SET 32'h00000008
      `define PPSG_CR_PWIDTH_OFFSET 4
      `define PPSG_CR_PWIDTH 32'hfffffff0
      `define ADDR_PPSG_CNTR_NSEC 5'h4
      `define ADDR_PPSG_CNTR_UTCLO 5'h8
      `define ADDR_PPSG_CNTR_UTCHI 5'hc
      `define ADDR_PPSG_ADJ_NSEC 5'h10
      `define ADDR_PPSG_ADJ_UTCLO 5'h14
      `define ADDR_PPSG_ADJ_UTCHI 5'h18
      `define ADDR_PPSG_ESCR 5'h1c
      `define ADDR_PPSG_CNTR_NSEC 6'h4
      `define ADDR_PPSG_CNTR_UTCLO 6'h8
      `define ADDR_PPSG_CNTR_UTCHI 6'hc
      `define ADDR_PPSG_ADJ_NSEC 6'h10
      `define ADDR_PPSG_ADJ_UTCLO 6'h14
      `define ADDR_PPSG_ADJ_UTCHI 6'h18
      `define ADDR_PPSG_ESCR 6'h1c
      `define PPSG_ESCR_SYNC_OFFSET 0
      `define PPSG_ESCR_SYNC 32'h00000001
      `define PPSG_ESCR_PPS_UNMASK_OFFSET 1
      ......@@ -30,3 +30,11 @@
      `define PPSG_ESCR_NSEC_SET 32'h00000020
      `define PPSG_ESCR_PPS_IN_TERM_OFFSET 6
      `define PPSG_ESCR_PPS_IN_TERM 32'h00000040
      `define PPSG_ESCR_TOD_IN_TERM_OFFSET 7
      `define PPSG_ESCR_TOD_IN_TERM 32'h00000080
      `define PPSG_ESCR_EXT_TAI_SYNC_OFFSET 8
      `define PPSG_ESCR_EXT_TAI_SYNC 32'h00000100
      `define PPSG_ESCR_EXT_TAI_READY_OFFSET 9
      `define PPSG_ESCR_EXT_TAI_READY 32'h00000200
      `define ADDR_PPSG_EXT_CNTR_UTCLO 6'h20
      `define ADDR_PPSG_EXT_CNTR_UTCHI 6'h24
      syn/cute_a7_ref_design/cute_a7_ref_design.xpr
      View file @ 50d6bf22
      ......@@ -3,7 +3,7 @@
      <!-- -->
      <!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -->
      <Project Version="7" Minor="38" Path="/home/yeym-thu/1-Workarea/1-WRN/7-cute-wr-released/cute-a7-wr/modules/wrpc/syn/cute_a7_ref_design/cute_a7_ref_design.xpr">
      <Project Version="7" Minor="38" Path="/home/hm/workspace/cute-a7-wr/modules/wrpc/syn/cute_a7_ref_design/cute_a7_ref_design.xpr">
      <DefaultLaunch Dir="$PRUNDIR"/>
      <Configuration>
      <Option Name="Id" Val="d14071a8a57c4979a2415fe945108260"/>
      ......@@ -280,13 +280,6 @@
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../board/cute_a7/wr_fdelay_ctrl.vhd">
      <FileInfo>
      <Attr Name="IsGlobalInclude" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_endpoint/wr_endpoint.vhd">
      <FileInfo>
      <Attr Name="IsGlobalInclude" Val="1"/>
      ......@@ -1141,14 +1134,14 @@
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gencores_pkg.vhd">
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd">
      <FileInfo>
      <Attr Name="IsGlobalInclude" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd">
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gencores_pkg.vhd">
      <FileInfo>
      <Attr Name="IsGlobalInclude" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      ......@@ -1235,6 +1228,67 @@
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/oserdes_8_to_1.v">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="implementation"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../top/cute_a7_ref_design/cute_a7_core.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/fine_delay_ctrl.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_edge_detect.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_sync.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/sma_config_wbgen2_pkg.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/sma_config_pkg.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/sma_config_wb_slave.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../modules/wr_sma_config/xwr_sma_config.vhd">
      <FileInfo>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../top/cute_a7_ref_design/cute_a7_ref_design.vhd">
      <FileInfo>
      <Attr Name="IsGlobalInclude" Val="1"/>
      ......@@ -1242,6 +1296,230 @@
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_reset.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_multichannel_frequency_meter.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_comparator.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_moving_average.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_sync_word_rd.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_simple_spi_master.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_delay_line.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_single_reset_gen.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_async_signals_input_stage.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/matrix_pkg.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_posedge.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_negedge.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_word_packer.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_sfp_i2c_adapter.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_big_adder.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_reset_multi_aasd.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <File Path="$PPRDIR/../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd">
      <FileInfo>
      <Attr Name="AutoDisabled" Val="1"/>
      <Attr Name="UsedIn" Val="synthesis"/>
      <Attr Name="UsedIn" Val="simulation"/>
      </FileInfo>
      </File>
      <Config>
      <Option Name="DesignMode" Val="RTL"/>
      <Option Name="TopModule" Val="cute_a7_ref_design"/>
      ......
      top/cute_a7_ref_design/cute_a7_core.vhd 0 → 100644
      View file @ 50d6bf22
      -------------------------------------------------------------------------------
      -- Title : WRPC Core for CUTE-WR-A7
      -- Project : WR PTP Core
      -- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
      -------------------------------------------------------------------------------
      -- File : cute_a7_core.vhd
      -- Author(s) : Hongming Li <lihm.thu@foxmail.com>
      -- Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : Tsinghua Univ. (DEP),CERN
      -- Standard : VHDL'93
      -------------------------------------------------------------------------------
      -- Description: WRPC Core for project on the CUTE-WR-A7.
      --
      -- This is a reference top HDL that instanciates the WR PTP Core together with
      -- its peripherals to be run on a CUTE-WR-A7 board.
      --
      -- There are two main usecases for this HDL file:
      -- * let new users easily synthesize a WR PTP Core bitstream that can be run on
      -- reference hardware
      -- * provide a reference top HDL file showing how the WRPC can be instantiated
      -- in HDL projects.
      --
      -- CUTE: https://www.ohwr.org/project/cute-wr-a7
      --
      -------------------------------------------------------------------------------
      -- Copyright (c) 2018 CERN
      -------------------------------------------------------------------------------
      -- GNU LESSER GENERAL PUBLIC LICENSE
      --
      -- This source file is free software; you can redistribute it
      -- and/or modify it under the terms of the GNU Lesser General
      -- Public License as published by the Free Software Foundation;
      -- either version 2.1 of the License,or (at your option) any
      -- later version.
      --
      -- This source is distributed in the hope that it will be
      -- useful,but WITHOUT ANY WARRANTY; without even the implied
      -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
      -- PURPOSE. See the GNU Lesser General Public License for more
      -- details.
      --
      -- You should have received a copy of the GNU Lesser General
      -- Public License along with this source; if not,download it
      -- from http://www.gnu.org/licenses/lgpl-2.1.html
      --
      -------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      library work;
      use work.gencores_pkg.all;
      use work.wrcore_pkg.all;
      use work.wishbone_pkg.all;
      use work.wr_fabric_pkg.all;
      use work.endpoint_pkg.all;
      use work.streamers_pkg.all;
      use work.wr_xilinx_pkg.all;
      use work.wr_board_pkg.all;
      use work.wishbone_pkg.all;
      use work.wr_cute_a7_pkg.all;
      use work.etherbone_pkg.all;
      library unisim;
      use unisim.vcomponents.all;
      entity cute_a7_core is
      generic(
      -- project name, NORMAL
      g_project_name : string := "NORMAL";
      g_dpram_initf : string := "../../../bin/wrpc/wrc_phy16.bram";
      g_board_name : string := "NM01";
      -- g_gtrefclk_src is 4bits integer
      -- each bit represents GTP ref clock source of each channel(phy)
      -- bit '0' selects PLL0(REF0)
      -- bit '1' selects PLL1(REF1)
      g_gtrefclk_src : std_logic_vector(3 downto 0):=(others=>'1');
      -- g_ref_clk_sel is 4bits integer
      -- each bit represents the clk_ref_o source of each channel(phy)
      -- bit '0' selects TXOUT
      -- bit '1' selects (GTP ref clock/2)
      g_ref_clk_sel : std_logic_vector(3 downto 0):=(others=>'1');
      g_num_output_clks : integer := 2;
      g_with_10M_output : boolean := false;
      g_with_external_clock_input : boolean := true;
      -- true: use inner pll
      -- false: use ext ad9516
      g_fabric_iface : t_board_fabric_iface := ETHERBONE;
      g_etherbone_sdb : t_sdb_device := c_etherbone_sdb;
      g_aux1_sdb : t_sdb_device := c_null_sdb;
      g_num_phys : integer := 2
      );
      port(
      SFP_RATE_SELECT_O : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_DISABLE_O : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_O_N : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_O_P : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_RX_I_N : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_RX_I_P : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_FAULT_I : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_LOS_I : in std_logic_vector(g_num_phys-1 downto 0);
      UART_RX_I : in std_logic;
      UART_TX_O : out std_logic;
      RESET_N : in std_logic;
      PPS_O_P : out std_logic;
      PPS_O_N : out std_logic;
      SYNC_CLK_10M_O_P : out std_logic;
      SYNC_CLK_10M_O_N : out std_logic;
      -- HOLD : in std_logic;
      VER0 : in std_logic;
      VER1 : in std_logic;
      VER2 : in std_logic;
      CLK_62M5_DMTD : in std_logic;
      FPGA_GCLK_P : in std_logic;
      FPGA_GCLK_N : in std_logic;
      MGTREFCLK1_P : in std_logic;
      MGTREFCLK1_N : in std_logic;
      OE_125M : out std_logic;
      MGTREFCLK0_P : in std_logic;
      MGTREFCLK0_N : in std_logic;
      DAC_LDAC_N : out std_logic;
      DAC_SCLK : out std_logic;
      DAC_SYNC_N : out std_logic;
      DAC_SDI : out std_logic;
      DAC_SDO : in std_logic;
      DAC_DMTD_LDAC_N : out std_logic;
      DAC_DMTD_SCLK : out std_logic;
      DAC_DMTD_SYNC_N : out std_logic;
      DAC_DMTD_SDI : out std_logic;
      DAC_DMTD_SDO : in std_logic;
      DELAY_EN : out std_logic_vector(0 downto 0);
      DELAY_SCLK : out std_logic_vector(0 downto 0);
      DELAY_SLOAD : out std_logic_vector(0 downto 0);
      DELAY_SDIN : out std_logic_vector(0 downto 0);
      -- DLY0_SE_FB : in std_logic;
      -- DLY1_SE_FB : in std_logic;
      QSPI_CS : out std_logic;
      QSPI_DQ0 : out std_logic;
      QSPI_DQ1 : in std_logic;
      --QSPI_DQ2 : in std_logic
      --QSPI_DQ3 : in std_logic
      ------------------------------------------
      -- AD9516 SPI
      ------------------------------------------
      PLL_CS : out std_logic;
      PLL_REFSEL : out std_logic;
      PLL_RESET : out std_logic;
      PLL_SCLK : out std_logic;
      PLL_SDO : out std_logic;
      PLL_SYNC : out std_logic;
      PLL_LOCK : in std_logic;
      PLL_SDI : in std_logic;
      PLL_STAT : in std_logic;
      -- 3-state-signals
      onewire_i : in std_logic;
      onewire_oen_o : out std_logic;
      sfp_scl_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=>'1');
      sfp_scl_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_sda_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=>'1');
      sfp_sda_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_det_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=>'1');
      -- timing
      pps_ext_i : in std_logic := '0';
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      clk_ext_i : in std_logic;
      clk_ext_mul_i : in std_logic;
      rst_62m5_n_o : out std_logic;
      clk_62m5_o : out std_logic;
      pps_csync_o : out std_logic;
      tm_time_valid_o : out std_logic;
      tm_tai_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      -- data
      eb_cfg_master_o : out t_wishbone_master_out;
      eb_cfg_master_i : in t_wishbone_master_in := cc_dummy_master_in;
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      LED_GREEN_O : out std_logic_vector(1 downto 0);
      LED_RED_O : out std_logic_vector(1 downto 0)
      );
      end cute_a7_core;
      architecture rtl of cute_a7_core is
      ------------------------------------------------------------------------------
      -- components declaration
      ------------------------------------------------------------------------------
      -- support AD5683
      component cute_a7_serial_dac_arb is
      generic(
      g_invert_sclk : boolean;
      g_num_data_bits : integer;
      g_num_extra_bits : integer);
      port(
      clk_i : in std_logic;
      rst_n_i : in std_logic;
      val_i : in std_logic_vector(g_num_data_bits-1 downto 0);
      load_i : in std_logic;
      dac_ldac_n_o : out std_logic;
      dac_clr_n_o : out std_logic;
      dac_sync_n_o : out std_logic;
      dac_sclk_o : out std_logic;
      dac_din_o : out std_logic);
      end component cute_a7_serial_dac_arb;
      function f_pick_ref_clock_rate (
      g_project_name : string
      ) return integer is
      begin
      return 62500000;
      end f_pick_ref_clock_rate;
      function f_pick_sys_clock_rate (
      g_project_name : string
      ) return integer is
      begin
      return 62500000;
      end f_pick_sys_clock_rate;
      function f_pick_ref_clock_hz (
      g_project_name : string
      ) return integer is
      begin
      return 62500000;
      end f_pick_ref_clock_hz;
      function f_pick_sys_clock_hz (
      g_project_name : string
      ) return integer is
      begin
      return 62500000;
      end f_pick_sys_clock_hz;
      function f_pick_ext_clock_rate (
      g_project_name : string
      ) return integer is
      begin
      return 10000000;
      end f_pick_ext_clock_rate;
      component reset_gen
      port (
      clk_i : in std_logic;
      rst_button_n_a_i : in std_logic;
      rst_pll_locked_i : in std_logic;
      rst_n_o : out std_logic);
      end component;
      signal VERSION : std_logic_vector(2 downto 0);
      ------------------------------------------------------------------------------
      -- Constants declaration
      ------------------------------------------------------------------------------
      signal local_reset_n : std_logic;
      signal pll_reset_n : std_logic;
      signal rst_aux_n : std_logic;
      signal clk_gtp_ref0_p_i : std_logic;
      signal clk_gtp_ref0_n_i : std_logic;
      signal clk_gtp_ref1_p_i : std_logic;
      signal clk_gtp_ref1_n_i : std_logic;
      signal clk_dmtd : std_logic;
      signal clk_dmtd_i : std_logic;
      signal clk_pll_dmtd_fb : std_logic;
      signal clk_pll_dmtd_o : std_logic;
      signal clk_sys : std_logic;
      signal clk_ref : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_ref_locked : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_serdes : std_logic;
      signal clk_serdes_i : std_logic;
      signal flash_spi_sclk_o : std_logic;
      signal flash_spi_ncs_o : std_logic;
      signal flash_spi_mosi_o : std_logic;
      signal flash_spi_miso_i : std_logic;
      signal dac_dpll_load_p1 : std_logic;
      signal dac_hpll_load_p1 : std_logic;
      signal dac_dpll_data : std_logic_vector(15 downto 0);
      signal dac_hpll_data : std_logic_vector(15 downto 0);
      signal dac_dpll_ldac_n_o : std_logic;
      signal dac_dpll_clr_n_o : std_logic;
      signal dac_dpll_sync_n_o : std_logic;
      signal dac_dpll_sclk_o : std_logic;
      signal dac_dpll_din_o : std_logic;
      signal dac_hpll_ldac_n_o : std_logic;
      signal dac_hpll_clr_n_o : std_logic;
      signal dac_hpll_sync_n_o : std_logic;
      signal dac_hpll_sclk_o : std_logic;
      signal dac_hpll_din_o : std_logic;
      signal onewire_in : std_logic_vector(1 downto 0);
      signal onewire_en : std_logic_vector(1 downto 0);
      signal uart_txd_o : std_logic;
      signal uart_rxd_i : std_logic;
      signal led_act : std_logic_vector(g_num_phys-1 downto 0);
      signal led_link : std_logic_vector(g_num_phys-1 downto 0);
      signal pps_p : std_logic;
      signal pps_led : std_logic;
      signal pps_csync : std_logic;
      signal pps_valid : std_logic;
      signal pps_unmask : std_logic;
      signal link_ok : std_logic_vector(g_num_phys-1 downto 0);
      signal sync_clk_10m_p : std_logic;
      signal sync_clk_10m_n : std_logic;
      signal tm_link_up : std_logic_vector(g_num_phys-1 downto 0);
      signal tm_time_valid : std_logic;
      signal tm_tai : std_logic_vector(39 downto 0);
      signal tm_cycles : std_logic_vector(27 downto 0);
      signal phy8_to_wrc : t_phy_8bits_to_wrc_array(g_num_phys-1 downto 0);
      signal phy8_from_wrc : t_phy_8bits_from_wrc_array(g_num_phys-1 downto 0);
      signal phy16_to_wrc : t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0);
      signal phy16_from_wrc : t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      signal delay_en_o : std_logic;
      signal delay_sclk_o : std_logic;
      signal delay_sdin_o : std_logic;
      signal delay_sload_o : std_logic;
      signal sync_data_o_p : std_logic_vector(1 downto 0);
      signal sync_data_o_n : std_logic_vector(1 downto 0);
      signal sma_slave_in : t_wishbone_slave_in;
      signal sma_slave_out : t_wishbone_slave_out;
      signal wb_slave_in : t_wishbone_slave_in;
      signal wb_slave_out : t_wishbone_slave_out;
      signal sfp_txp_o : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_txn_o : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_rxp_i : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_rxn_i : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_tx_fault : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_los : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_tx_disable : std_logic_vector(g_num_phys-1 downto 0);
      signal aux_master_out : t_wishbone_master_out;
      signal aux_master_in : t_wishbone_master_in;
      signal aux1_master_out : t_wishbone_master_out;
      signal aux1_master_in : t_wishbone_master_in;
      signal wb_eth_master_out : t_wishbone_master_out;
      signal wb_eth_master_in : t_wishbone_master_in;
      signal eb_cfg_master_out : t_wishbone_master_out;
      signal eb_cfg_master_in : t_wishbone_master_in := cc_dummy_master_in;
      signal wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      signal wrf_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      signal eb_wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal eb_wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      signal eb_wrf_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal eb_wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      signal clk_ext : std_logic:='0';
      signal clk_ext_mul : std_logic:='0';
      signal clk_ext_mul_locked : std_logic:='0';
      signal clk_ext_stopped : std_logic:='0';
      signal clk_ext_locked_i : std_logic:='0';
      signal clk_ext_stopped_i : std_logic:='0';
      signal clk_ext_rst : std_logic:='0';
      signal ext_pll_mosi : std_logic:='0';
      signal ext_pll_miso : std_logic:='0';
      signal ext_pll_sck : std_logic:='0';
      signal ext_pll_cs_n : std_logic:='0';
      signal ext_pll_sync_n : std_logic:='0';
      signal ext_pll_reset_n : std_logic:='0';
      signal ppsin_term : std_logic;
      signal todin_term : std_logic;
      begin
      u_reset_gen: reset_gen
      port map (
      clk_i => clk_dmtd,
      rst_button_n_a_i => RESET_N,
      rst_pll_locked_i => '1',
      rst_n_o => pll_reset_n
      );
      local_reset_n <= pll_reset_n;
      -----------------------------------------------------------------------------
      -- The WR PTP core with optional fabric interface attached
      -----------------------------------------------------------------------------
      cmp_board_cute_a7 : xwrc_board_cute_a7
      generic map (
      g_num_phys => g_num_phys,
      g_aux_sdb => c_sma_config_sdb,
      g_aux1_sdb => g_aux1_sdb,
      g_etherbone_sdb => g_etherbone_sdb,
      g_fabric_iface => g_fabric_iface,
      g_dpram_initf => g_dpram_initf,
      g_with_10M_output => g_with_10M_output,
      g_with_external_clock_input => g_with_external_clock_input,
      g_board_name => g_board_name,
      g_flash_secsz_kb => 64, -- default for N25Q128
      g_flash_sdbfs_baddr => 16#760000#, -- default for N25Q128
      g_phys_uart => TRUE,
      g_virtual_uart => FALSE,
      g_ep_rxbuf_size => 1024,
      g_tx_runt_padding => TRUE,
      g_dpram_size => 131072/4,
      g_softpll_enable_debugger => FALSE,
      g_pcs_16bit => TRUE,
      g_interface_mode => PIPELINED,
      g_address_granularity => BYTE,
      g_ref_clock_rate => f_pick_ref_clock_rate(g_project_name),
      g_sys_clock_rate => f_pick_sys_clock_rate(g_project_name),
      g_ref_clock_hz => f_pick_ref_clock_hz(g_project_name),
      g_sys_clock_hz => f_pick_sys_clock_hz(g_project_name),
      g_ext_clock_rate => f_pick_ext_clock_rate(g_project_name)
      )
      port map (
      clk_sys_i => clk_sys,
      clk_dmtd_i => clk_dmtd,
      clk_ref_i => clk_ref(0),
      clk_ext_i => clk_ext,
      clk_ext_mul_i => clk_ext_mul,
      clk_ext_mul_locked_i => clk_ext_mul_locked,
      clk_ext_stopped_i => clk_ext_stopped,
      clk_ext_rst_o => clk_ext_rst,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term,
      todin_term_o => todin_term,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      rst_n_i => local_reset_n,
      dac_hpll_load_p1_o => dac_hpll_load_p1,
      dac_hpll_data_o => dac_hpll_data,
      dac_dpll_load_p1_o => dac_dpll_load_p1,
      dac_dpll_data_o => dac_dpll_data,
      phy16_o => phy16_from_wrc,
      phy16_i => phy16_to_wrc,
      scl_o => open,
      scl_i => '0',
      sda_o => open,
      sda_i => '0',
      sfp_scl_o => sfp_scl_o,
      sfp_scl_i => sfp_scl_i,
      sfp_sda_o => sfp_sda_o,
      sfp_sda_i => sfp_sda_i,
      sfp_det_i => sfp_det_i,
      flash_spi_sclk_o => flash_spi_sclk_o,
      flash_spi_ncs_o => flash_spi_ncs_o,
      flash_spi_mosi_o => flash_spi_mosi_o,
      flash_spi_miso_i => flash_spi_miso_i,
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o,
      owr_pwren_o => open,
      owr_en_o => onewire_en,
      owr_i => onewire_in,
      pll_mosi_o => open,
      pll_miso_i => '0',
      pll_sck_o => open,
      pll_cs_n_o => open,
      pll_sync_n_o => open,
      pll_reset_n_o => open,
      ext_pll_mosi_o => ext_pll_mosi,
      ext_pll_miso_i => ext_pll_miso,
      ext_pll_sck_o => ext_pll_sck,
      ext_pll_cs_n_o => ext_pll_cs_n,
      ext_pll_sync_n_o => ext_pll_sync_n,
      ext_pll_reset_n_o => ext_pll_reset_n,
      wb_slave_i => wb_slave_in,
      wb_slave_o => wb_slave_out,
      aux_master_o => aux_master_out,
      aux_master_i => aux_master_in,
      aux1_master_o => aux1_master_out,
      aux1_master_i => aux1_master_in,
      eb_cfg_master_i => eb_cfg_master_in,
      eb_cfg_master_o => eb_cfg_master_out,
      wrf_src_o => wrf_src_out,
      wrf_src_i => wrf_src_in,
      wrf_snk_o => wrf_snk_out,
      wrf_snk_i => wrf_snk_in,
      eb_wrf_src_o => eb_wrf_src_out,
      eb_wrf_src_i => eb_wrf_src_in,
      eb_wrf_snk_o => eb_wrf_snk_out,
      eb_wrf_snk_i => eb_wrf_snk_in,
      wb_eth_master_o => wb_eth_master_out,
      wb_eth_master_i => wb_eth_master_in,
      rst_aux_n_o => rst_aux_n,
      aux_diag_i => (others => (others => '0')),
      aux_diag_o => open,
      tm_dac_value_o => open,
      tm_dac_wr_o => open,
      tm_clk_aux_lock_en_i => (others => '0'),
      tm_clk_aux_locked_o => open,
      timestamps_o => open,
      timestamps_ack_i => (others=>'1'),
      abscal_txts_o => open,
      abscal_rxts_o => open,
      fc_tx_pause_req_i => (others => '0'),
      fc_tx_pause_delay_i => (others => '0'),
      fc_tx_pause_ready_o => open,
      tm_link_up_o => tm_link_up,
      tm_time_valid_o => tm_time_valid,
      tm_tai_o => tm_tai,
      tm_cycles_o => tm_cycles,
      led_act_o => led_act(g_num_phys-1 downto 0),
      led_link_o => led_link(g_num_phys-1 downto 0),
      btn1_i => '1',
      btn2_i => '1',
      pps_csync_o => pps_csync,
      pps_p_o => pps_p,
      pps_led_o => pps_led,
      pps_valid_o => pps_valid,
      pps_unmask_o => pps_unmask,
      sync_clk_10m_o_p => sync_clk_10m_p,
      sync_clk_10m_o_n => sync_clk_10m_n,
      link_ok_o => link_ok
      );
      -- port 0 <-> port 1
      wrf_src_in(0) <= wrf_snk_out(1);
      wrf_snk_in(0) <= wrf_src_out(1);
      wrf_src_in(1) <= wrf_snk_out(0);
      wrf_snk_in(1) <= wrf_src_out(0);
      cmp_xwrc_platform : xwrc_platform_xilinx
      generic map (
      g_fpga_family => "artix7",
      g_use_default_plls => FALSE,
      g_gtrefclk_src => g_gtrefclk_src,
      g_ref_clk_sel => g_ref_clk_sel,
      g_with_external_clock_input => g_with_external_clock_input,
      g_num_phys => g_num_phys,
      g_simulation => 0)
      port map (
      areset_n_i => local_reset_n,
      clk_ext_i => clk_ext_i,
      clk_gtp_ref0_p_i => clk_gtp_ref0_p_i,
      clk_gtp_ref0_n_i => clk_gtp_ref0_n_i,
      clk_gtp_ref1_p_i => clk_gtp_ref1_p_i,
      clk_gtp_ref1_n_i => clk_gtp_ref1_n_i,
      clk_gtp_ref0_locked_i => '1',
      clk_gtp_ref1_locked_i => '1',
      clk_125m_pllref_i => '0',
      sfp_txp_o => sfp_txp_o,
      sfp_txn_o => sfp_txn_o,
      sfp_rxp_i => sfp_rxp_i,
      sfp_rxn_i => sfp_rxn_i,
      sfp_tx_fault_i => sfp_tx_fault,
      sfp_los_i => sfp_los,
      sfp_tx_disable_o => sfp_tx_disable,
      clk_sys_i => clk_ref(0),
      clk_sys_o => clk_sys,
      clk_ref_o => clk_ref,
      clk_ref_locked_o => clk_ref_locked,
      clk_dmtd_i => clk_dmtd_i,
      clk_dmtd_o => clk_dmtd,
      clk_ext_o => clk_ext,
      clk_ext_mul_i => clk_ext_mul_i,
      clk_ext_mul_o => clk_ext_mul,
      clk_ext_locked_i => clk_ext_locked_i,
      clk_ext_mul_locked_o => clk_ext_mul_locked,
      clk_ext_stopped_i => clk_ext_stopped_i,
      clk_ext_mul_stopped_o => clk_ext_stopped,
      clk_ext_rst_i => clk_ext_rst,
      phy16_o => phy16_to_wrc,
      phy16_i => phy16_from_wrc
      );
      U_Main_DAC : cute_a7_serial_dac_arb
      generic map (
      g_invert_sclk => FALSE,
      g_num_data_bits => 16,
      g_num_extra_bits => 8)
      port map (
      clk_i => clk_sys,
      rst_n_i => local_reset_n,
      val_i => dac_dpll_data,
      load_i => dac_dpll_load_p1,
      dac_sync_n_o => dac_dpll_sync_n_o,
      dac_ldac_n_o => dac_dpll_ldac_n_o,
      dac_clr_n_o => dac_dpll_clr_n_o,
      dac_sclk_o => dac_dpll_sclk_o,
      dac_din_o => dac_dpll_din_o
      );
      U_DMTD_DAC : cute_a7_serial_dac_arb
      generic map (
      g_invert_sclk => FALSE,
      g_num_data_bits => 16,
      g_num_extra_bits => 8)
      port map (
      clk_i => clk_sys,
      rst_n_i => local_reset_n,
      val_i => dac_hpll_data,
      load_i => dac_hpll_load_p1,
      dac_sync_n_o => dac_hpll_sync_n_o,
      dac_ldac_n_o => dac_hpll_ldac_n_o,
      dac_clr_n_o => dac_hpll_clr_n_o,
      dac_sclk_o => dac_hpll_sclk_o,
      dac_din_o => dac_hpll_din_o
      );
      U_SMA_CTRL: xwr_sma_config
      generic map(
      g_interface_mode => PIPELINED,
      g_address_granularity => BYTE
      )
      port map(
      rst_n_i => local_reset_n,
      clk_sys_i => clk_sys,
      clk_serdes_i => clk_serdes_i,
      pps_csync_i => pps_csync,
      pps_valid_i => pps_unmask,
      tm_tai_i => tm_tai,
      sync_data_o_p => sync_data_o_p,
      sync_data_o_n => sync_data_o_n,
      fdly_en_o => delay_en_o,
      fdly_sload_o => delay_sload_o,
      fdly_sdin_o => delay_sdin_o,
      fdly_sclk_o => delay_sclk_o,
      slave_i => sma_slave_in,
      slave_o => sma_slave_out
      );
      sma_slave_in <= aux_master_out;
      aux_master_in <= sma_slave_out;
      SYNC_CLK_10M_O_P <= sync_data_o_p(0);
      SYNC_CLK_10M_O_N <= sync_data_o_n(0);
      PPS_O_P <= sync_data_o_p(1);
      PPS_O_N <= sync_data_o_n(1);
      DELAY_EN(0) <= delay_en_o;
      DELAY_SCLK(0) <= delay_sclk_o;
      DELAY_SDIN(0) <= delay_sdin_o;
      DELAY_SLOAD(0) <= delay_sload_o;
      VERSION <= VER2 & VER1 & VER0;
      OE_125M <= '0';
      LED_GREEN_O(0) <= pps_valid when led_link(0) = '1' else '0';
      LED_GREEN_O(1) <= tm_time_valid when led_link(1) = '1' else '0';
      LED_RED_O(0) <= led_act(0);
      LED_RED_O(1) <= led_act(1);
      clk_gtp_ref0_p_i <= MGTREFCLK0_P;
      clk_gtp_ref0_n_i <= MGTREFCLK0_N;
      clk_gtp_ref1_p_i <= MGTREFCLK1_P;
      clk_gtp_ref1_n_i <= MGTREFCLK1_N;
      SFP_RATE_SELECT_O <= (others=>'1');
      SFP_TX_O_P <= sfp_txp_o;
      SFP_TX_O_N <= sfp_txn_o;
      SFP_TX_DISABLE_O <= sfp_tx_disable;
      sfp_rxp_i <= SFP_RX_I_P;
      sfp_rxn_i <= SFP_RX_I_N;
      sfp_tx_fault <= SFP_FAULT_I;
      sfp_los <= SFP_LOS_I;
      UART_TX_O <= uart_txd_o;
      uart_rxd_i <= UART_RX_I;
      DAC_SYNC_N <= dac_dpll_sync_n_o;
      DAC_LDAC_N <= dac_dpll_ldac_n_o;
      DAC_SCLK <= dac_dpll_sclk_o;
      DAC_SDI <= dac_dpll_din_o;
      DAC_DMTD_SYNC_N <= dac_hpll_sync_n_o;
      DAC_DMTD_LDAC_N <= dac_hpll_ldac_n_o;
      DAC_DMTD_SCLK <= dac_hpll_sclk_o;
      DAC_DMTD_SDI <= dac_hpll_din_o;
      QSPI_CS <= flash_spi_ncs_o;
      QSPI_DQ0 <= flash_spi_mosi_o;
      flash_spi_miso_i <= QSPI_DQ1;
      cmp_clk_dmtd_i : IBUFG
      port map (
      O => clk_dmtd_i,
      I => CLK_62M5_DMTD);
      cmp_clk_serdes : IBUFGDS
      generic map (
      DIFF_TERM => true, -- Differential Termination
      IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT"
      )
      port map (
      O => clk_serdes,
      I => FPGA_GCLK_P,
      IB => FPGA_GCLK_N
      );
      cmp_clk_serdes_buf_i : BUFG
      port map (
      O => clk_serdes_i,
      I => clk_serdes
      );
      PLL_RESET <= pll_reset_n;
      PLL_REFSEL <= '0'; -- ref1 (signal low) , ref2 (signal high)
      PLL_SYNC <= '1';
      cmp_pll_ctrl: wr_pll_ctrl
      generic map (
      g_project_name => g_project_name,
      g_spi_clk_freq => x"00000004" -- 1 for 25M, 4 for 62.5M
      )
      port map (
      clk_i => clk_dmtd,
      rst_n_i => pll_reset_n,
      pll_lock_i => PLL_LOCK,
      pll_status_i => PLL_STAT,
      pll_cs_n_o => PLL_CS,
      pll_sck_o => PLL_SCLK,
      pll_mosi_o => PLL_SDO,
      pll_miso_i => PLL_SDI,
      -- spi controller status
      done_o => open
      );
      rst_62m5_n_o <= rst_aux_n;
      clk_62m5_o <= clk_sys;
      pps_csync_o <= pps_csync;
      tm_time_valid_o <= pps_unmask;
      tm_tai_o <= tm_tai;
      tm_cycles_o <= tm_cycles;
      eb_cfg_master_in <= eb_cfg_master_i;
      eb_wrf_src_in <= eb_wrf_src_i;
      eb_wrf_snk_in <= eb_wrf_snk_i;
      eb_cfg_master_o <= eb_cfg_master_out;
      eb_wrf_src_o <= eb_wrf_src_out;
      eb_wrf_snk_o <= eb_wrf_snk_out;
      onewire_oen_o <= onewire_en(0);
      onewire_in(0) <= onewire_i;
      onewire_in(1) <= '1';
      end rtl;
      top/cute_a7_ref_design/cute_a7_ref_design.mmi deleted 100644 → 0
      View file @ fecc11ee
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X0Y13">
      <DataWidth MSB="0" LSB="0"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X0Y16">
      <DataWidth MSB="1" LSB="1"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X0Y15">
      <DataWidth MSB="2" LSB="2"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X0Y11">
      <DataWidth MSB="3" LSB="3"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X0Y12">
      <DataWidth MSB="4" LSB="4"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X1Y10">
      <DataWidth MSB="5" LSB="5"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y14">
      <DataWidth MSB="6" LSB="6"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X0Y14">
      <DataWidth MSB="7" LSB="7"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X0Y3">
      <DataWidth MSB="8" LSB="8"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X1Y2">
      <DataWidth MSB="9" LSB="9"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X0Y2">
      <DataWidth MSB="10" LSB="10"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X1Y4">
      <DataWidth MSB="11" LSB="11"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X1Y3">
      <DataWidth MSB="12" LSB="12"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X0Y4">
      <DataWidth MSB="13" LSB="13"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X0Y6">
      <DataWidth MSB="14" LSB="14"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X0Y5">
      <DataWidth MSB="15" LSB="15"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X1Y7">
      <DataWidth MSB="16" LSB="16"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X0Y7">
      <DataWidth MSB="17" LSB="17"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X2Y7">
      <DataWidth MSB="18" LSB="18"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X0Y8">
      <DataWidth MSB="19" LSB="19"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X0Y9">
      <DataWidth MSB="20" LSB="20"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X1Y5">
      <DataWidth MSB="21" LSB="21"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y6">
      <DataWidth MSB="22" LSB="22"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X2Y6">
      <DataWidth MSB="23" LSB="23"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X2Y12">
      <DataWidth MSB="24" LSB="24"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X2Y13">
      <DataWidth MSB="25" LSB="25"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X1Y9">
      <DataWidth MSB="26" LSB="26"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X2Y9">
      <DataWidth MSB="27" LSB="27"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X2Y10">
      <DataWidth MSB="28" LSB="28"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X2Y8">
      <DataWidth MSB="29" LSB="29"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y8">
      <DataWidth MSB="30" LSB="30"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X2Y11">
      <DataWidth MSB="31" LSB="31"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a35tcsg325-2"/>
      </Config>
      </MemInfo>
      top/cute_a7_ref_design/cute_a7_ref_design.vhd
      View file @ 50d6bf22
      -------------------------------------------------------------------------------
      -- Title : WRPC reference design for cuteA7
      -- Title : WRPC reference design for CUTE-WR-A7
      -- Project : WR PTP Core
      -- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
      -------------------------------------------------------------------------------
      -- File : cute_a7_ref_design.vhd
      -- Author(s) : Hongming Li <lihm.thu@foxmail.com>
      -- Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
      -- Company : Tsinghua Univ. (DEP),CERN
      -- Company : DEP, Tsinghua Univ.
      -- CERN
      -- Standard : VHDL'93
      -------------------------------------------------------------------------------
      -- Description: Top-level file for the WRPC reference design on the CUTE.
      -- Description: Top-level file for the WRPC reference design on the CUTE-WR-A7.
      --
      -- This is a reference top HDL that instanciates the WR PTP Core together with
      -- its peripherals to be run on a CUTE board.
      -- its peripherals to be run on a CUTE-WR-A7 board.
      --
      -- There are two main usecases for this HDL file:
      -- * let new users easily synthesize a WR PTP Core bitstream that can be run on
      ......@@ -20,7 +21,7 @@
      -- * provide a reference top HDL file showing how the WRPC can be instantiated
      -- in HDL projects.
      --
      -- CUTE: https://www.ohwr.org/projects/cute-wr-dp
      -- CUTE: https://www.ohwr.org/project/cute-wr-a7
      --
      -------------------------------------------------------------------------------
      -- Copyright (c) 2018 CERN
      ......@@ -69,28 +70,31 @@ entity cute_a7_ref_design is
      generic(
      -- project name, NORMAL
      g_project_name : string := "NORMAL";
      -- g_gtrefclk_src is 4bits integer
      -- each bit represents GTP ref clock source of each channel(phy)
      -- bit '0' selects PLL0(REF0)
      -- bit '1' selects PLL1(REF1)
      g_gtrefclk_src : std_logic_vector(3 downto 0):=(others=>'1');
      -- g_ref_clk_sel is 4bits integer
      -- each bit represents the clk_ref_o source of each channel(phy)
      -- bit '0' selects TXOUT
      -- bit '1' selects (GTP ref clock/2)
      g_ref_clk_sel : std_logic_vector(3 downto 0):=(others=>'1');
      g_num_output_clks : integer := 2;
      g_with_10M_output : boolean := true;
      g_num_phys : integer := 2;
      g_fabric_iface : t_board_fabric_iface := ETHERBONE;
      g_dpram_initf : string := "../../../../bin/wrpc/wrc_phy16.bram"
      g_num_phys : integer := 2
      );
      port(
      -- HOLD : in std_logic;
      -- SFP_RATE_SELECT_O : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_DISABLE_O : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_O_N : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_TX_O_P : out std_logic_vector(g_num_phys-1 downto 0);
      SFP_RX_I_N : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_RX_I_P : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_FAULT_I : in std_logic_vector(g_num_phys-1 downto 0);
      SFP_LOS_I : in std_logic_vector(g_num_phys-1 downto 0);
      UART_RX_I : in std_logic;
      UART_TX_O : out std_logic;
      RESET_N : in std_logic;
      LOCK : out std_logic;
      PPS_O_P : out std_logic;
      PPS_O_N : out std_logic;
      SYNC_CLK_10M_O_P : out std_logic;
      SYNC_CLK_10M_O_N : out std_logic;
      VER0 : in std_logic;
      VER1 : in std_logic;
      VER2 : in std_logic;
      ONE_WIRE : inout std_logic;
      CLK_62M5_DMTD : in std_logic;
      FPGA_GCLK_P : in std_logic;
      FPGA_GCLK_N : in std_logic;
      ......@@ -99,57 +103,25 @@ port(
      OE_125M : out std_logic;
      MGTREFCLK0_P : in std_logic;
      MGTREFCLK0_N : in std_logic;
      DAC_LDAC_N : out std_logic;
      DAC_SCLK : out std_logic;
      DAC_SYNC_N : out std_logic;
      DAC_SDI : out std_logic;
      DAC_SDO : in std_logic;
      DAC_DMTD_LDAC_N : out std_logic;
      DAC_DMTD_SCLK : out std_logic;
      DAC_DMTD_SYNC_N : out std_logic;
      DAC_DMTD_SDI : out std_logic;
      DAC_DMTD_SDO : in std_logic;
      -------------------------------------------------------------------------
      -- GTP0 pins
      -------------------------------------------------------------------------
      -- SFP_RATE_SELECT : out std_logic_vector(1 downto 0);
      SFP_DISABLE_O : out std_logic_vector(1 downto 0);
      SFP_O_N : out std_logic_vector(1 downto 0);
      SFP_O_P : out std_logic_vector(1 downto 0);
      SFP_I_N : in std_logic_vector(1 downto 0);
      SFP_I_P : in std_logic_vector(1 downto 0);
      SFP_FAULT_I : in std_logic_vector(1 downto 0);
      SFP_LOS_I : in std_logic_vector(1 downto 0);
      SFP_MOD_DEF0_I : in std_logic_vector(1 downto 0);
      SFP_MOD_DEF1_IO : inout std_logic_vector(1 downto 0);
      SFP_MOD_DEF2_IO : inout std_logic_vector(1 downto 0);
      led_green_o : out std_logic_vector(1 downto 0);
      led_red_o : out std_logic_vector(1 downto 0);
      RX : in std_logic;
      TX : out std_logic;
      TEST : in std_logic;
      -- CLK_25M_BAK : in std_logic;
      SYNC_DATA0_N : out std_logic;
      SYNC_DATA0_P : out std_logic;
      SYNC_DATA1_N : out std_logic;
      SYNC_DATA1_P : out std_logic;
      DELAY_EN : out std_logic;
      DELAY_SCLK : out std_logic;
      DELAY_SLOAD : out std_logic;
      DELAY_SDIN : out std_logic;
      DELAY_EN : out std_logic_vector(0 downto 0);
      DELAY_SCLK : out std_logic_vector(0 downto 0);
      DELAY_SLOAD : out std_logic_vector(0 downto 0);
      DELAY_SDIN : out std_logic_vector(0 downto 0);
      QSPI_CS : out std_logic;
      QSPI_DQ0 : out std_logic;
      QSPI_DQ1 : in std_logic;
      --QSPI_DQ2 : in std_logic
      --QSPI_DQ3 : in std_logic
      ------------------------------------------
      -- AD9516 SPI
      ------------------------------------------
      ......@@ -161,325 +133,187 @@ port(
      PLL_SYNC : out std_logic;
      PLL_LOCK : in std_logic;
      PLL_SDI : in std_logic;
      PLL_STAT : in std_logic
      );
      end cute_a7_ref_design;
      architecture rtl of cute_a7_ref_design is
      PLL_STAT : in std_logic;
      -- support AD5683
      component cute_a7_serial_dac_arb is
      generic(
      g_invert_sclk : boolean;
      g_num_data_bits : integer;
      g_num_extra_bits : integer);
      port(
      clk_i : in std_logic;
      rst_n_i : in std_logic;
      val_i : in std_logic_vector(g_num_data_bits-1 downto 0);
      load_i : in std_logic;
      dac_ldac_n_o : out std_logic;
      dac_clr_n_o : out std_logic;
      dac_sync_n_o : out std_logic;
      dac_sclk_o : out std_logic;
      dac_din_o : out std_logic);
      end component cute_a7_serial_dac_arb;
      component reset_gen
      port (
      clk_i : in std_logic;
      rst_button_n_a_i : in std_logic;
      rst_pll_locked_i : in std_logic;
      rst_n_o : out std_logic);
      end component;
      signal VERSION : std_logic_vector(2 downto 0);
      ------------------------------------------------------------------------------
      -- Constants declaration
      ------------------------------------------------------------------------------
      signal local_reset_n : std_logic;
      signal pll_reset_n : std_logic;
      signal pll_done : std_logic;
      signal pllout_fb_ddmtd : std_logic;
      signal clk_dmtd : std_logic;
      signal clk_dmtd_i : std_logic;
      signal clk_pll_dmtd_fb : std_logic;
      signal clk_pll_dmtd_o : std_logic;
      signal clk_sys : std_logic;
      signal clk_ref : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_ref_locked : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_serdes : std_logic;
      signal clk_serdes_i : std_logic;
      signal sfp_scl_o : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_scl_i : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_sda_o : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_sda_i : std_logic_vector(g_num_phys-1 downto 0);
      signal sfp_det : std_logic_vector(g_num_phys-1 downto 0);
      signal flash_ncs_o : std_logic;
      signal flash_qspi_dq0 : std_logic;
      signal flash_qspi_dq1 : std_logic;
      signal dac_main_load : std_logic;
      signal dac_ddmtd_load : std_logic;
      signal dac_main_data : std_logic_vector(15 downto 0);
      signal dac_ddmtd_data : std_logic_vector(15 downto 0);
      signal onewire_in : std_logic_vector(1 downto 0);
      signal onewire_en : std_logic_vector(1 downto 0);
      -- 3-state-signals
      ONE_WIRE : inout std_logic;
      SFP_MOD_DEF0_I : in std_logic_vector(1 downto 0);
      SFP_MOD_DEF1_IO : inout std_logic_vector(1 downto 0);
      SFP_MOD_DEF2_IO : inout std_logic_vector(1 downto 0);
      signal uart_txd_o : std_logic;
      signal uart_rxd_i : std_logic;
      signal led_act : std_logic_vector(g_num_phys-1 downto 0);
      signal led_link : std_logic_vector(g_num_phys-1 downto 0);
      signal pps : std_logic;
      signal pps_led : std_logic;
      signal pps_csync : std_logic;
      signal link_ok : std_logic_vector(g_num_phys-1 downto 0);
      signal sync_data_p_o : std_logic;
      signal sync_data_n_o : std_logic;
      signal tm_time_valid : std_logic;
      -- RESV_I : in std_logic;
      -- RESV_O : out std_logic;
      LED_GREEN_O : out std_logic_vector(1 downto 0);
      LED_RED_O : out std_logic_vector(1 downto 0)
      signal phy16_to_wrc : t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0);
      signal phy16_from_wrc : t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      );
      end cute_a7_ref_design;
      signal delay_en_o : std_logic;
      signal delay_sclk_o : std_logic;
      signal delay_sdin_o : std_logic;
      signal delay_sload_o : std_logic;
      signal wb_slave_in : t_wishbone_slave_in;
      signal wb_slave_out : t_wishbone_slave_out;
      architecture rtl of cute_a7_ref_design is
      signal wb_eth_master_out : t_wishbone_master_out;
      signal wb_eth_master_in : t_wishbone_master_in;
      signal eb_cfg_master_out : t_wishbone_master_out;
      signal eb_wrf_src_out : t_wrf_source_out_array(2-1 downto 0);
      signal eb_wrf_snk_out : t_wrf_sink_out_array(2-1 downto 0);
      signal eb_cfg_master_in : t_wishbone_master_in:=c_DUMMY_WB_MASTER_IN;
      signal eb_wrf_src_in : t_wrf_source_in_array(2-1 downto 0):=(others=>c_dummy_src_in);
      signal eb_wrf_snk_in : t_wrf_sink_in_array(2-1 downto 0):=(others=>c_dummy_snk_in);
      signal rst_sys_n : STD_LOGIC;
      signal clk_sys : STD_LOGIC;
      signal pps_csync : STD_LOGIC;
      signal tm_time_valid : STD_LOGIC;
      signal tm_tai : STD_LOGIC_VECTOR ( 39 downto 0 );
      signal tm_cycles : STD_LOGIC_VECTOR ( 27 downto 0 );
      signal onewire_i : std_logic;
      signal onewire_oen_o : std_logic;
      signal clk_ext_i : std_logic:='0';
      signal pps_ext_i : std_logic:='0';
      signal clk_ext_mul_i : std_logic:='0';
      signal sfp_scl_i : std_logic_vector(2-1 downto 0);
      signal sfp_scl_o : std_logic_vector(2-1 downto 0);
      signal sfp_sda_i : std_logic_vector(2-1 downto 0);
      signal sfp_sda_o : std_logic_vector(2-1 downto 0);
      signal sfp_det_i : std_logic_vector(2-1 downto 0);
      signal clkfb : std_logic;
      signal clk_125M : std_logic;
      signal clk_125M_bufg : std_logic;
      signal dcm_locked : std_logic;
      begin
      cmp_clk_dmtd_i : IBUFG
      port map (
      O => clk_dmtd,
      I => CLK_62M5_DMTD);
      cmp_clk_serdes : IBUFGDS
      u_cute_a7_core: entity work.cute_a7_core
      generic map (
      DIFF_TERM => true, -- Differential Termination
      IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
      IOSTANDARD => "DEFAULT"
      g_project_name => "NORMAL",
      g_dpram_initf => "../../../../bin/wrpc/wrc_phy16.bram",
      g_board_name => "NM01",
      g_gtrefclk_src => (others=>'1'),
      g_ref_clk_sel => (others=>'1'),
      g_num_output_clks => 2,
      g_with_10M_output => false,
      g_with_external_clock_input => false,
      g_fabric_iface => ETHERBONE,
      g_etherbone_sdb => c_etherbone_sdb,
      g_aux1_sdb => c_null_sdb,
      g_num_phys => 2
      )
      port map (
      O => clk_serdes,
      I => FPGA_GCLK_P,
      IB => FPGA_GCLK_N
      );
      cmp_clk_serdes_buf_i : BUFG
      port map (
      O => clk_serdes_i,
      I => clk_serdes
      );
      u_reset_gen: reset_gen
      port map (
      clk_i => clk_dmtd,
      rst_button_n_a_i => TEST,
      rst_pll_locked_i => '1',
      rst_n_o => pll_reset_n
      );
      local_reset_n <= pll_reset_n;
      PLL_RESET <= pll_reset_n;
      PLL_REFSEL <= '0'; -- ref1 (signal low) , ref2 (signal high)
      PLL_SYNC <= '1';
      cmp_pll_ctrl: wr_pll_ctrl
      generic map (
      g_spi_clk_freq => x"00000004" -- 1 for 25M, 4 for 62.5M
      )
      port map (
      clk_i => clk_dmtd,
      rst_n_i => pll_reset_n,
      pll_lock_i => PLL_LOCK,
      pll_status_i => PLL_STAT,
      pll_cs_n_o => PLL_CS,
      pll_sck_o => PLL_SCLK,
      pll_mosi_o => PLL_SDO,
      pll_miso_i => PLL_SDI,
      -- spi controller status
      done_o => open
      port map(
      VER0 => VER0,
      VER1 => VER1,
      VER2 => VER2,
      CLK_62M5_DMTD => CLK_62M5_DMTD,
      FPGA_GCLK_P => FPGA_GCLK_P,
      FPGA_GCLK_N => FPGA_GCLK_N,
      MGTREFCLK1_P => MGTREFCLK1_P,
      MGTREFCLK1_N => MGTREFCLK1_N,
      OE_125M => OE_125M,
      MGTREFCLK0_P => MGTREFCLK0_P,
      MGTREFCLK0_N => MGTREFCLK0_N,
      DAC_LDAC_N => DAC_LDAC_N,
      DAC_SCLK => DAC_SCLK,
      DAC_SYNC_N => DAC_SYNC_N,
      DAC_SDI => DAC_SDI,
      DAC_SDO => DAC_SDO,
      DAC_DMTD_LDAC_N => DAC_DMTD_LDAC_N,
      DAC_DMTD_SCLK => DAC_DMTD_SCLK,
      DAC_DMTD_SYNC_N => DAC_DMTD_SYNC_N,
      DAC_DMTD_SDI => DAC_DMTD_SDI,
      DAC_DMTD_SDO => DAC_DMTD_SDO,
      SFP_TX_DISABLE_O => SFP_TX_DISABLE_O,
      SFP_TX_O_N => SFP_TX_O_N,
      SFP_TX_O_P => SFP_TX_O_P,
      SFP_RX_I_N => SFP_RX_I_N,
      SFP_RX_I_P => SFP_RX_I_P,
      SFP_FAULT_I => SFP_FAULT_I,
      SFP_LOS_I => SFP_LOS_I,
      LED_GREEN_O => LED_GREEN_O,
      LED_RED_O => LED_RED_O,
      UART_RX_I => UART_RX_I,
      UART_TX_O => UART_TX_O,
      RESET_N => RESET_N,
      SYNC_CLK_10M_O_N => SYNC_CLK_10M_O_N,
      SYNC_CLK_10M_O_P => SYNC_CLK_10M_O_P,
      PPS_O_N => PPS_O_N,
      PPS_O_P => PPS_O_P,
      DELAY_EN => DELAY_EN,
      DELAY_SCLK => DELAY_SCLK,
      DELAY_SLOAD => DELAY_SLOAD,
      DELAY_SDIN => DELAY_SDIN,
      QSPI_CS => QSPI_CS,
      QSPI_DQ0 => QSPI_DQ0,
      QSPI_DQ1 => QSPI_DQ1,
      PLL_CS => PLL_CS,
      PLL_REFSEL => PLL_REFSEL,
      PLL_RESET => PLL_RESET,
      PLL_SCLK => PLL_SCLK,
      PLL_SDO => PLL_SDO,
      PLL_SYNC => PLL_SYNC,
      PLL_LOCK => PLL_LOCK,
      PLL_SDI => PLL_SDI,
      PLL_STAT => PLL_STAT,
      clk_ext_i => clk_ext_i,
      pps_ext_i => pps_ext_i,
      clk_ext_mul_i => clk_ext_mul_i,
      onewire_i => onewire_i,
      onewire_oen_o => onewire_oen_o,
      sfp_scl_i => sfp_scl_i,
      sfp_scl_o => sfp_scl_o,
      sfp_sda_i => sfp_sda_i,
      sfp_sda_o => sfp_sda_o,
      sfp_det_i => sfp_det_i,
      rst_62m5_n_o => rst_sys_n,
      clk_62m5_o => clk_sys,
      pps_csync_o => pps_csync,
      tm_time_valid_o => tm_time_valid,
      tm_tai_o => tm_tai,
      tm_cycles_o => tm_cycles,
      ext_tai_valid_p_i => '0',
      ext_tai_i => (others=>'0'),
      ext_tai_ready_i => '0',
      eb_cfg_master_o => eb_cfg_master_out,
      eb_cfg_master_i => eb_cfg_master_in,
      eb_wrf_src_o => eb_wrf_src_out,
      eb_wrf_src_i => eb_wrf_src_in,
      eb_wrf_snk_o => eb_wrf_snk_out,
      eb_wrf_snk_i => eb_wrf_snk_in
      );
      -----------------------------------------------------------------------------
      -- The WR PTP core with optional fabric interface attached
      -----------------------------------------------------------------------------
      cmp_board_cute_a7 : xwrc_board_cute_a7
      generic map (
      g_num_phys => g_num_phys,
      g_aux1_sdb => c_null_sdb,
      g_etherbone_sdb => c_etherbone_sdb,
      g_fabric_iface => g_fabric_iface,
      g_with_10M_output => g_with_10M_output,
      g_dpram_initf => g_dpram_initf,
      g_with_external_clock_input => false
      mmcm: MMCME2_BASE
      generic map(
      clkin1_period => 16.0,
      clkfbout_mult_f => 16.0,
      clkout1_divide => integer(1000.0 / 125.00)
      )
      port map (
      clk_sys_i => clk_sys,
      clk_dmtd_i => clk_dmtd,
      clk_ref_i => clk_ref(0),
      rst_n_i => local_reset_n,
      dac_hpll_load_p1_o => dac_ddmtd_load,
      dac_hpll_data_o => dac_ddmtd_data,
      dac_dpll_load_p1_o => dac_main_load,
      dac_dpll_data_o => dac_main_data,
      phy16_o => phy16_from_wrc,
      phy16_i => phy16_to_wrc,
      sfp_scl_o => sfp_scl_o,
      sfp_scl_i => sfp_scl_i,
      sfp_sda_o => sfp_sda_o,
      sfp_sda_i => sfp_sda_i,
      sfp_det_i => sfp_det,
      wb_eth_master_o => wb_eth_master_out,
      wb_eth_master_i => wb_eth_master_in,
      wb_slave_i => wb_slave_in,
      wb_slave_o => wb_slave_out,
      flash_spi_ncs_o => flash_ncs_o,
      flash_spi_mosi_o => flash_qspi_dq0,
      flash_spi_miso_i => flash_qspi_dq1,
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o,
      owr_en_o => onewire_en,
      owr_i => onewire_in,
      led_act_o => led_act(g_num_phys-1 downto 0),
      led_link_o => led_link(g_num_phys-1 downto 0),
      pps_o => pps,
      pps_csync_o => pps_csync,
      pps_led_o => pps_led,
      link_ok_o => link_ok,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      tm_time_valid_o => tm_time_valid
      port map(
      clkin1 => clk_sys,
      clkfbin => clkfb,
      clkfbout => clkfb,
      clkout1 => clk_125M,
      clkout2 => open,
      clkout3 => open,
      locked => dcm_locked,
      rst => '0',
      pwrdwn => '0'
      );
      wb_eth_master_in <= wb_slave_out;
      wb_slave_in <= wb_eth_master_out;
      cmp_xwrc_platform : xwrc_platform_xilinx
      generic map (
      g_fpga_family => "artix7",
      g_with_external_clock_input => false,
      g_use_default_plls => false,
      g_gtrefclk_src => g_gtrefclk_src,
      g_ref_clk_sel => g_ref_clk_sel,
      g_num_phys => g_num_phys,
      g_simulation => 0)
      port map (
      areset_n_i => local_reset_n,
      clk_gtp_ref0_p_i => MGTREFCLK0_P,
      clk_gtp_ref0_n_i => MGTREFCLK0_N,
      clk_gtp_ref1_p_i => MGTREFCLK1_P,
      clk_gtp_ref1_n_i => MGTREFCLK1_N,
      clk_gtp_ref0_locked_i => '1',
      clk_gtp_ref1_locked_i => '1',
      sfp_txp_o => SFP_O_P(g_num_phys-1 downto 0),
      sfp_txn_o => SFP_O_N(g_num_phys-1 downto 0),
      sfp_rxp_i => SFP_I_P(g_num_phys-1 downto 0),
      sfp_rxn_i => SFP_I_N(g_num_phys-1 downto 0),
      sfp_tx_fault_i => SFP_FAULT_I(g_num_phys-1 downto 0),
      sfp_los_i => SFP_LOS_I(g_num_phys-1 downto 0),
      sfp_tx_disable_o => SFP_DISABLE_O(g_num_phys-1 downto 0),
      clk_sys_i => clk_ref(0),
      clk_sys_o => clk_sys,
      clk_ref_o => clk_ref,
      clk_ref_locked_o => clk_ref_locked,
      phy16_o => phy16_to_wrc,
      phy16_i => phy16_from_wrc
      bufgclk_125m: BUFG port map(
      i => clk_125M,
      o => clk_125M_bufg
      );
      U_Main_DAC : cute_a7_serial_dac_arb
      generic map (
      g_invert_sclk => FALSE,
      g_num_data_bits => 16,
      g_num_extra_bits => 8)
      port map (
      clk_i => clk_sys,
      rst_n_i => local_reset_n,
      val_i => dac_main_data,
      load_i => dac_main_load,
      dac_sync_n_o => DAC_SYNC_N,
      dac_ldac_n_o => DAC_LDAC_N,
      dac_clr_n_o => open,
      dac_sclk_o => DAC_SCLK,
      dac_din_o => DAC_SDI);
      U_DMTD_DAC : cute_a7_serial_dac_arb
      generic map (
      g_invert_sclk => FALSE,
      g_num_data_bits => 16,
      g_num_extra_bits => 8)
      port map (
      clk_i => clk_sys,
      rst_n_i => local_reset_n,
      val_i => dac_ddmtd_data,
      load_i => dac_ddmtd_load,
      dac_sync_n_o => DAC_DMTD_SYNC_N,
      dac_ldac_n_o => DAC_DMTD_LDAC_N,
      dac_clr_n_o => open,
      dac_sclk_o => DAC_DMTD_SCLK,
      dac_din_o => DAC_DMTD_SDI);
      gen_SFP_I2C: for i in 0 to g_num_phys-1 generate
      SFP_MOD_DEF1_IO(i) <= '0' when sfp_scl_o(i) = '0' else 'Z';
      SFP_MOD_DEF2_IO(i) <= '0' when sfp_sda_o(i) = '0' else 'Z';
      sfp_scl_i(i) <= SFP_MOD_DEF1_IO(i);
      sfp_sda_i(i) <= SFP_MOD_DEF2_IO(i);
      sfp_det(i) <= SFP_MOD_DEF0_I(i);
      sfp_det_i(i) <= SFP_MOD_DEF0_I(i);
      end generate gen_SFP_I2C;
      SYNC_DATA_0_OBUF : OBUFDS
      port map(
      O => SYNC_DATA1_P,
      OB => SYNC_DATA1_N,
      I => pps);
      SYNC_DATA0_P <= sync_data_p_o;
      SYNC_DATA0_N <= sync_data_n_o;
      DELAY_EN <= delay_en_o;
      DELAY_SCLK <= delay_sclk_o;
      DELAY_SDIN <= delay_sdin_o;
      DELAY_SLOAD <= delay_sload_o;
      U_FDLY_CTRL: wr_fdelay_ctrl
      generic map(
      fdelay_ch0 => (others=>'0'),
      fdelay_ch1 => (others=>'0')
      )
      port map(
      rst_sys_n_i => local_reset_n,
      clk_sys_i => clk_sys,
      delay_en_o => delay_en_o,
      delay_sload_o => delay_sload_o,
      delay_sdin_o => delay_sdin_o,
      delay_sclk_o => delay_sclk_o
      );
      QSPI_CS <= flash_ncs_o;
      QSPI_DQ0 <= flash_qspi_dq0;
      flash_qspi_dq1 <= QSPI_DQ1;
      ONE_WIRE <= '0' when onewire_en(0) = '1' else 'Z';
      onewire_in(0) <= ONE_WIRE;
      onewire_in(1) <= '1';
      VERSION <= VER2 & VER1 & VER0;
      OE_125M <= '0';
      TX <= uart_txd_o;
      uart_rxd_i <= RX;
      led_green_o(0) <= tm_time_valid when led_link(0) = '1' else '0';
      led_green_o(1) <= tm_time_valid when led_link(1) = '1' else '0';
      led_red_o <= led_act;
      ONE_WIRE <= '0' when onewire_oen_o = '1' else 'Z';
      onewire_i <= ONE_WIRE;
      LOCK <= tm_time_valid;
      end rtl;
      top/cute_a7_ref_design/cute_a7_ref_design.xdc
      View file @ 50d6bf22
      #####################################################
      #################### Reset Button ###################
      #####################################################
      # set_property PACKAGE_PIN H18 [get_ports BUTTON]
      # set_property IOSTANDARD LVCMOS25 [get_ports BUTTON]
      #####################################################
      #################### Version ########################
      #####################################################
      ......@@ -61,38 +67,38 @@ set_property IOSTANDARD LVCMOS33 [get_ports DAC_DMTD_SDI]
      #####################################################
      #################### GTP Signals#####################
      #####################################################
      set_property PACKAGE_PIN U17 [get_ports {SFP_DISABLE_O[0]}]
      set_property PACKAGE_PIN U17 [get_ports {SFP_TX_DISABLE_O[0]}]
      set_property PACKAGE_PIN V17 [get_ports {SFP_FAULT_I[0]}]
      set_property PACKAGE_PIN P18 [get_ports {SFP_LOS_I[0]}]
      set_property PACKAGE_PIN R18 [get_ports {SFP_MOD_DEF0_I[0]}]
      set_property PACKAGE_PIN T18 [get_ports {SFP_MOD_DEF1_IO[0]}]
      set_property PACKAGE_PIN T17 [get_ports {SFP_MOD_DEF2_IO[0]}]
      set_property PACKAGE_PIN A3 [get_ports {SFP_I_N[0]}]
      set_property PACKAGE_PIN A4 [get_ports {SFP_I_P[0]}]
      set_property PACKAGE_PIN F1 [get_ports {SFP_O_N[0]}]
      set_property PACKAGE_PIN F2 [get_ports {SFP_O_P[0]}]
      set_property PACKAGE_PIN A3 [get_ports {SFP_RX_I_N[0]}]
      set_property PACKAGE_PIN A4 [get_ports {SFP_RX_I_P[0]}]
      set_property PACKAGE_PIN F1 [get_ports {SFP_TX_O_N[0]}]
      set_property PACKAGE_PIN F2 [get_ports {SFP_TX_O_P[0]}]
      #set_property PACKAGE_PIN N16 [get_ports { SFP_RATE_SELECT[0] } ]
      set_property PACKAGE_PIN M15 [get_ports {SFP_DISABLE_O[1]}]
      set_property PACKAGE_PIN M15 [get_ports {SFP_TX_DISABLE_O[1]}]
      set_property PACKAGE_PIN L14 [get_ports {SFP_FAULT_I[1]}]
      set_property PACKAGE_PIN P15 [get_ports {SFP_LOS_I[1]}]
      set_property PACKAGE_PIN T12 [get_ports {SFP_MOD_DEF0_I[1]}]
      set_property PACKAGE_PIN N14 [get_ports {SFP_MOD_DEF1_IO[1]}]
      set_property PACKAGE_PIN M14 [get_ports {SFP_MOD_DEF2_IO[1]}]
      set_property PACKAGE_PIN G3 [get_ports {SFP_I_N[1]}]
      set_property PACKAGE_PIN G4 [get_ports {SFP_I_P[1]}]
      set_property PACKAGE_PIN B1 [get_ports {SFP_O_N[1]}]
      set_property PACKAGE_PIN B2 [get_ports {SFP_O_P[1]}]
      set_property PACKAGE_PIN G3 [get_ports {SFP_RX_I_N[1]}]
      set_property PACKAGE_PIN G4 [get_ports {SFP_RX_I_P[1]}]
      set_property PACKAGE_PIN B1 [get_ports {SFP_TX_O_N[1]}]
      set_property PACKAGE_PIN B2 [get_ports {SFP_TX_O_P[1]}]
      #set_property PACKAGE_PIN R13 [get_ports { SFP_RATE_SELECT[1] } ]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_DISABLE_O[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_TX_DISABLE_O[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_FAULT_I[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_LOS_I[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_MOD_DEF0_I[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_MOD_DEF1_IO[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_MOD_DEF2_IO[0]}]
      #set_property IOSTANDARD LVCMOS33 [get_ports {SFP_RATE_SELECT[0]} ]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_DISABLE_O[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_TX_DISABLE_O[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_FAULT_I[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_LOS_I[1]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {SFP_MOD_DEF0_I[1]}]
      ......@@ -103,51 +109,53 @@ set_property IOSTANDARD LVCMOS33 [get_ports {SFP_MOD_DEF2_IO[1]}]
      #####################################################
      ######################## LED ######################
      #####################################################
      set_property PACKAGE_PIN H14 [get_ports {led_green_o[0]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {led_green_o[0]}]
      set_property PACKAGE_PIN G14 [get_ports {led_red_o[0]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {led_red_o[0]}]
      set_property PACKAGE_PIN H17 [get_ports {led_green_o[1]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {led_green_o[1]}]
      set_property PACKAGE_PIN E18 [get_ports {led_red_o[1]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {led_red_o[1]}]
      set_property PACKAGE_PIN H14 [get_ports {LED_GREEN_O[0]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {LED_GREEN_O[0]}]
      set_property PACKAGE_PIN G14 [get_ports {LED_RED_O[0]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {LED_RED_O[0]}]
      set_property PACKAGE_PIN H17 [get_ports {LED_GREEN_O[1]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {LED_GREEN_O[1]}]
      set_property PACKAGE_PIN E18 [get_ports {LED_RED_O[1]}]
      set_property IOSTANDARD LVCMOS25 [get_ports {LED_RED_O[1]}]
      #####################################################
      ###################### UART #########################
      #####################################################
      set_property PACKAGE_PIN R16 [get_ports RX]
      set_property PACKAGE_PIN R17 [get_ports TX]
      set_property PACKAGE_PIN K15 [get_ports TEST]
      set_property PACKAGE_PIN R16 [get_ports UART_RX_I]
      set_property PACKAGE_PIN R17 [get_ports UART_TX_O]
      set_property PACKAGE_PIN K15 [get_ports RESET_N]
      set_property PACKAGE_PIN B17 [get_ports LOCK]
      #set_property PACKAGE_PIN T15 [get_ports CLK_25M_BAK]
      set_property IOSTANDARD LVCMOS33 [get_ports RX]
      set_property IOSTANDARD LVCMOS33 [get_ports TX]
      set_property IOSTANDARD LVCMOS33 [get_ports TEST]
      set_property IOSTANDARD LVCMOS33 [get_ports UART_RX_I]
      set_property IOSTANDARD LVCMOS33 [get_ports UART_TX_O]
      set_property IOSTANDARD LVCMOS33 [get_ports RESET_N]
      set_property IOSTANDARD LVCMOS25 [get_ports LOCK]
      #set_property IOSTANDARD LVCMOS33 CLK_25M_BAK
      #####################################################
      ###################### TIME #########################
      #####################################################
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_DATA0_N]
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_DATA0_P]
      set_property PACKAGE_PIN B9 [get_ports SYNC_DATA0_P]
      set_property PACKAGE_PIN A9 [get_ports SYNC_DATA0_N]
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_DATA1_N]
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_DATA1_P]
      set_property PACKAGE_PIN D8 [get_ports SYNC_DATA1_P]
      set_property PACKAGE_PIN C8 [get_ports SYNC_DATA1_N]
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_CLK_10M_O_N]
      set_property IOSTANDARD LVDS_25 [get_ports SYNC_CLK_10M_O_P]
      set_property PACKAGE_PIN B9 [get_ports SYNC_CLK_10M_O_P]
      set_property PACKAGE_PIN A9 [get_ports SYNC_CLK_10M_O_N]
      set_property IOSTANDARD LVDS_25 [get_ports PPS_O_N]
      set_property IOSTANDARD LVDS_25 [get_ports PPS_O_P]
      set_property PACKAGE_PIN D8 [get_ports PPS_O_P]
      set_property PACKAGE_PIN C8 [get_ports PPS_O_N]
      #####################################################
      ################### Delay Chip#######################
      #####################################################
      set_property PACKAGE_PIN J18 [get_ports DELAY_EN]
      set_property PACKAGE_PIN K18 [get_ports DELAY_SCLK]
      set_property PACKAGE_PIN M16 [get_ports DELAY_SLOAD]
      set_property PACKAGE_PIN J14 [get_ports DELAY_SDIN]
      set_property IOSTANDARD LVCMOS33 [get_ports DELAY_EN]
      set_property IOSTANDARD LVCMOS33 [get_ports DELAY_SCLK]
      set_property IOSTANDARD LVCMOS33 [get_ports DELAY_SLOAD]
      set_property IOSTANDARD LVCMOS33 [get_ports DELAY_SDIN]
      set_property PACKAGE_PIN J18 [get_ports {DELAY_EN[0]}]
      set_property PACKAGE_PIN K18 [get_ports {DELAY_SCLK[0]}]
      set_property PACKAGE_PIN M16 [get_ports {DELAY_SLOAD[0]}]
      set_property PACKAGE_PIN J14 [get_ports {DELAY_SDIN[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {DELAY_EN[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {DELAY_SCLK[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {DELAY_SLOAD[0]}]
      set_property IOSTANDARD LVCMOS33 [get_ports {DELAY_SDIN[0]}]
      #####################################################
      ###################### FLASH ########################
      ......@@ -190,17 +198,20 @@ set_property IOSTANDARD LVCMOS33 [get_ports PLL_SDI]
      set_property IOSTANDARD LVCMOS33 [get_ports PLL_STAT]
      ## NORMAL
      #create_clock -period 100.000 -name clk_ext_p_i -waveform {0.000 50.000} [get_ports clk_ext_p_i]
      create_clock -period 8.000 -name CLK_62M5_DMTD -waveform {0.000 4.000} [get_ports CLK_62M5_DMTD]
      create_clock -period 16.000 -name CLK_62M5_DMTD -waveform {0.000 8.000} [get_ports CLK_62M5_DMTD]
      create_clock -period 8.000 -name MGTREFCLK0_P -waveform {0.000 4.000} [get_ports MGTREFCLK0_P]
      create_clock -period 8.000 -name MGTREFCLK1_P -waveform {0.000 4.000} [get_ports MGTREFCLK1_P]
      create_clock -period 4.000 -name clk_serdes_i -waveform {0.000 2.000} [get_ports FPGA_GCLK_P]
      create_clock -period 16.000 -name RXOUTCLK0 -waveform {0.000 8.000} [get_pins {cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[0].GT_INST/gtpe2_i/RXOUTCLK}]
      create_clock -period 16.000 -name TXOUTCLK0 -waveform {0.000 8.000} [get_pins {cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[0].GT_INST/gtpe2_i/TXOUTCLK}]
      create_clock -period 16.000 -name RXOUTCLK1 -waveform {0.000 8.000} [get_pins {cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[1].GT_INST/gtpe2_i/RXOUTCLK}]
      create_clock -period 16.000 -name TXOUTCLK1 -waveform {0.000 8.000} [get_pins {cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[1].GT_INST/gtpe2_i/TXOUTCLK}]
      create_clock -period 8.000 -name clk_serdes_i -waveform {0.000 4.000} [get_ports FPGA_GCLK_P]
      create_clock -period 16.000 -name RXOUTCLK0 -waveform {0.000 8.000} [get_pins {u_cute_a7_core/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[0].GT_INST/gtpe2_i/RXOUTCLK}]
      create_clock -period 16.000 -name TXOUTCLK0 -waveform {0.000 8.000} [get_pins {u_cute_a7_core/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[0].GT_INST/gtpe2_i/TXOUTCLK}]
      create_clock -period 16.000 -name RXOUTCLK1 -waveform {0.000 8.000} [get_pins {u_cute_a7_core/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[1].GT_INST/gtpe2_i/RXOUTCLK}]
      create_clock -period 16.000 -name TXOUTCLK1 -waveform {0.000 8.000} [get_pins {u_cute_a7_core/cmp_xwrc_platform/gen_phy_artix7.cmp_gtp/U_GTP_INST/gen_GT_INTS[1].GT_INST/gtpe2_i/TXOUTCLK}]
      create_clock -period 16.000 -name clk_gtp_ref1_div2 -waveform {0.000 8.000} -add [get_nets -hierarchical *clk_gtp_ref1_div2*]
      # set_property ASYNC_REG true [get_nets {u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_Aligner_EXT/cnt_in_gray_xd_reg_n_0_[*]}]
      set_property IOB TRUE [get_ports SYNC_DATA1_P]
      # set_property IOB TRUE [get_ports SYNC_CLK_10M_O_P]
      # set_property IOB TRUE [get_ports PPS_O_P]
      set_clock_groups -name g1 -asynchronous -group CLK_62M5_DMTD -group MGTREFCLK0_P
      set_clock_groups -name g2 -asynchronous -group CLK_62M5_DMTD -group MGTREFCLK1_P
      ......@@ -208,50 +219,56 @@ set_clock_groups -name g3 -asynchronous -group CLK_62M5_DMTD -group RXOUTCLK0
      set_clock_groups -name g4 -asynchronous -group CLK_62M5_DMTD -group RXOUTCLK1
      set_clock_groups -name g5 -asynchronous -group CLK_62M5_DMTD -group TXOUTCLK0
      set_clock_groups -name g6 -asynchronous -group CLK_62M5_DMTD -group TXOUTCLK1
      #set_clock_groups -name g8 -asynchronous -group CLK_62M5_DMTD -group clk_serdes_i
      set_clock_groups -name g8 -asynchronous -group CLK_62M5_DMTD -group clk_serdes_i
      set_clock_groups -name g9 -asynchronous -group CLK_62M5_DMTD -group clk_gtp_ref1_div2
      set_clock_groups -name g10 -asynchronous -group clk_gtp_ref1_div2 -group CLK_62M5_DMTD
      set_clock_groups -name g13 -asynchronous -group clk_serdes_i -group clk_gtp_ref1_div2
      set_clock_groups -name g15 -asynchronous -group RXOUTCLK0 -group clk_gtp_ref1_div2
      set_clock_groups -name g16 -asynchronous -group RXOUTCLK1 -group clk_gtp_ref1_div2
      set_property ASYNC_REG true [get_cells {u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property LOC RAMB36_X2Y14 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7]
      set_property LOC RAMB36_X1Y17 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6]
      set_property LOC RAMB36_X2Y17 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5]
      set_property LOC RAMB36_X2Y15 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4]
      set_property LOC RAMB36_X1Y14 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3]
      set_property LOC RAMB36_X2Y16 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2]
      set_property LOC RAMB36_X1Y18 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1]
      set_property LOC RAMB36_X1Y15 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0]
      set_property LOC RAMB36_X1Y5 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7]
      set_property LOC RAMB36_X2Y5 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6]
      set_property LOC RAMB36_X2Y6 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5]
      set_property LOC RAMB36_X1Y6 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4]
      set_property LOC RAMB36_X2Y7 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3]
      set_property LOC RAMB36_X2Y4 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2]
      set_property LOC RAMB36_X1Y4 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1]
      set_property LOC RAMB36_X1Y3 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0]
      set_property LOC RAMB36_X1Y10 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7]
      set_property LOC RAMB36_X0Y10 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6]
      set_property LOC RAMB36_X0Y11 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5]
      set_property LOC RAMB36_X0Y12 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4]
      set_property LOC RAMB36_X1Y7 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3]
      set_property LOC RAMB36_X0Y8 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2]
      set_property LOC RAMB36_X0Y9 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1]
      set_property LOC RAMB36_X0Y7 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0]
      set_property LOC RAMB36_X2Y13 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7]
      set_property LOC RAMB36_X2Y11 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6]
      set_property LOC RAMB36_X2Y12 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5]
      set_property LOC RAMB36_X1Y8 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4]
      set_property LOC RAMB36_X1Y9 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3]
      set_property LOC RAMB36_X2Y8 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2]
      set_property LOC RAMB36_X2Y9 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1]
      set_property LOC RAMB36_X1Y13 [get_cells u_cute_a7_core/cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0]
      #set_max_delay -from [get_clocks MGTREFCLK1_P] -to [get_clocks clk_serdes_i] 3.200
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d0_reg}]
      set_property ASYNC_REG true [get_cells {cmp_board_cute_a7/cmp_xwr_core/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/gen_builtin.U_Sampler/gen_straight.clk_i_d3_reg}]
      set_property CONFIG_VOLTAGE 3.3 [current_design]
      set_property CFGBVS VCCO [current_design]
      # set_property BITSTREAM.CONFIG.PERSIST YES [current_design]
      set_false_path -from [get_clocks -of_objects [get_pins cmp_xwrc_platform/gen_phy_artix7.cmp_gtp_ref1_dedicated_clk/ODIV2]] -to [get_clocks clk_serdes_i]
      set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
      set_property BITSTREAM.CONFIG.TIMER_CFG 32'h002625A0 [current_design]
      set_property LOC RAMB36_X0Y13 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7]
      set_property LOC RAMB36_X0Y16 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6]
      set_property LOC RAMB36_X0Y15 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5]
      set_property LOC RAMB36_X0Y11 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4]
      set_property LOC RAMB36_X0Y12 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3]
      set_property LOC RAMB36_X1Y10 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2]
      set_property LOC RAMB36_X1Y14 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1]
      set_property LOC RAMB36_X0Y14 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0]
      set_property LOC RAMB36_X0Y3 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7]
      set_property LOC RAMB36_X1Y2 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6]
      set_property LOC RAMB36_X0Y2 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5]
      set_property LOC RAMB36_X1Y4 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4]
      set_property LOC RAMB36_X1Y3 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3]
      set_property LOC RAMB36_X0Y4 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2]
      set_property LOC RAMB36_X0Y6 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1]
      set_property LOC RAMB36_X0Y5 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0]
      set_property LOC RAMB36_X1Y7 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7]
      set_property LOC RAMB36_X0Y7 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6]
      set_property LOC RAMB36_X2Y7 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5]
      set_property LOC RAMB36_X0Y8 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4]
      set_property LOC RAMB36_X0Y9 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3]
      set_property LOC RAMB36_X1Y5 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2]
      set_property LOC RAMB36_X1Y6 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1]
      set_property LOC RAMB36_X2Y6 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0]
      set_property LOC RAMB36_X2Y12 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7]
      set_property LOC RAMB36_X2Y13 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6]
      set_property LOC RAMB36_X1Y9 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5]
      set_property LOC RAMB36_X2Y9 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4]
      set_property LOC RAMB36_X2Y10 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3]
      set_property LOC RAMB36_X2Y8 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2]
      set_property LOC RAMB36_X1Y8 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1]
      set_property LOC RAMB36_X2Y11 [get_cells cmp_board_cute_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0]
      top/cute_a7_ref_design/cute_a7_ref_design_35t.mmi 0 → 100644
      View file @ 50d6bf22
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y14"> <DataWidth MSB="0" LSB="0"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 --><BitLane MemType="RAMB32" Placement="X1Y17"> <DataWidth MSB="1" LSB="1"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y17"> <DataWidth MSB="2" LSB="2"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 --><BitLane MemType="RAMB32" Placement="X2Y15"> <DataWidth MSB="4" LSB="4"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y14"> <DataWidth MSB="5" LSB="5"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y16"> <DataWidth MSB="6" LSB="6"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y18"> <DataWidth MSB="7" LSB="7"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y15"> <DataWidth MSB="3" LSB="3"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y5"> <DataWidth MSB="8" LSB="8"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y5"> <DataWidth MSB="9" LSB="9"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y6"> <DataWidth MSB="10" LSB="10"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y6"> <DataWidth MSB="11" LSB="11"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 --><BitLane MemType="RAMB32" Placement="X2Y7"> <DataWidth MSB="12" LSB="12"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y4"> <DataWidth MSB="13" LSB="13"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y4"> <DataWidth MSB="14" LSB="14"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y3"> <DataWidth MSB="15" LSB="15"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y10"> <DataWidth MSB="16" LSB="16"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 --><BitLane MemType="RAMB32" Placement="X0Y10"> <DataWidth MSB="17" LSB="17"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 --><BitLane MemType="RAMB32" Placement="X0Y11"> <DataWidth MSB="18" LSB="18"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 --><BitLane MemType="RAMB32" Placement="X0Y12"> <DataWidth MSB="19" LSB="19"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y7"> <DataWidth MSB="20" LSB="20"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 --><BitLane MemType="RAMB32" Placement="X0Y8"> <DataWidth MSB="21" LSB="21"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 --><BitLane MemType="RAMB32" Placement="X0Y9"> <DataWidth MSB="22" LSB="22"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 --><BitLane MemType="RAMB32" Placement="X0Y7"> <DataWidth MSB="23" LSB="23"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y13"> <DataWidth MSB="24" LSB="24"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y11"> <DataWidth MSB="25" LSB="25"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y12"> <DataWidth MSB="26" LSB="26"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y8"> <DataWidth MSB="27" LSB="27"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y9"> <DataWidth MSB="28" LSB="28"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y8"> <DataWidth MSB="29" LSB="29"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 --><BitLane MemType="RAMB32" Placement="X2Y9"> <DataWidth MSB="30" LSB="30"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y13"> <DataWidth MSB="31" LSB="31"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a35tcsg325-2"/>
      </Config>
      </MemInfo>
      top/cute_a7_ref_design/cute_a7_ref_design_50t.mmi 0 → 100644
      View file @ 50d6bf22
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y14"> <DataWidth MSB="0" LSB="0"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 --><BitLane MemType="RAMB32" Placement="X1Y17"> <DataWidth MSB="1" LSB="1"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y17"> <DataWidth MSB="2" LSB="2"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 --><BitLane MemType="RAMB32" Placement="X2Y15"> <DataWidth MSB="4" LSB="4"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y14"> <DataWidth MSB="5" LSB="5"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y16"> <DataWidth MSB="6" LSB="6"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y18"> <DataWidth MSB="7" LSB="7"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y15"> <DataWidth MSB="3" LSB="3"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y5"> <DataWidth MSB="8" LSB="8"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y5"> <DataWidth MSB="9" LSB="9"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y6"> <DataWidth MSB="10" LSB="10"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y6"> <DataWidth MSB="11" LSB="11"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 --><BitLane MemType="RAMB32" Placement="X2Y7"> <DataWidth MSB="12" LSB="12"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y4"> <DataWidth MSB="13" LSB="13"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y4"> <DataWidth MSB="14" LSB="14"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y3"> <DataWidth MSB="15" LSB="15"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y10"> <DataWidth MSB="16" LSB="16"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 --><BitLane MemType="RAMB32" Placement="X0Y10"> <DataWidth MSB="17" LSB="17"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 --><BitLane MemType="RAMB32" Placement="X0Y11"> <DataWidth MSB="18" LSB="18"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 --><BitLane MemType="RAMB32" Placement="X0Y12"> <DataWidth MSB="19" LSB="19"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y7"> <DataWidth MSB="20" LSB="20"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 --><BitLane MemType="RAMB32" Placement="X0Y8"> <DataWidth MSB="21" LSB="21"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 --><BitLane MemType="RAMB32" Placement="X0Y9"> <DataWidth MSB="22" LSB="22"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 --><BitLane MemType="RAMB32" Placement="X0Y7"> <DataWidth MSB="23" LSB="23"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y13"> <DataWidth MSB="24" LSB="24"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y11"> <DataWidth MSB="25" LSB="25"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y12"> <DataWidth MSB="26" LSB="26"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y8"> <DataWidth MSB="27" LSB="27"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y9"> <DataWidth MSB="28" LSB="28"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y8"> <DataWidth MSB="29" LSB="29"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 --><BitLane MemType="RAMB32" Placement="X2Y9"> <DataWidth MSB="30" LSB="30"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y13"> <DataWidth MSB="31" LSB="31"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a50tcsg325-2"/>
      </Config>
      </MemInfo>
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