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White Rabbit core collection
Commit 50d6bf22 authored by li hongming's avatar li hongming
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support new cute-wr-a7 board

parent fecc11ee
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      .gitignore
      View file @ 50d6bf22
      ......@@ -19,4 +19,5 @@ doc/
      Makefile
      *.xml
      xgui/
      *.orig
      \ No newline at end of file
      *_bd.bmm
      *.orig
      bin/wrpc/wrc_phy16.bram
      View file @ 50d6bf22
      This diff is collapsed.
      board/common/xwrc_board_common.vhd
      View file @ 50d6bf22
      This diff is collapsed.
      board/cute/wr_cute_pkg.vhd
      View file @ 50d6bf22
      ......@@ -186,7 +186,7 @@ package wr_cute_pkg is
      addr_first => x"0000000000000000",
      addr_last => x"00000000000000ff",
      product => (
      vendor_id => x"0000000000001103", -- thu
      vendor_id => x"0000000000746875", -- thu
      device_id => x"c0413599",
      version => x"00000001",
      date => x"20160424",
      ......
      board/cute_a7/Manifest.py
      View file @ 50d6bf22
      ......@@ -4,8 +4,7 @@ files = [
      "wr_cute_a7_pkg.vhd",
      "cute_a7_serial_dac_arb.vhd",
      "cute_a7_serial_dac.vhd",
      "xwrc_board_cute_a7.vhd",
      "wr_fdelay_ctrl.vhd"
      "xwrc_board_cute_a7.vhd"
      ]
      modules = {
      ......
      board/cute_a7/wr_cute_a7_pkg.vhd
      View file @ 50d6bf22
      ......@@ -53,7 +53,7 @@ generic(
      g_verbose : boolean := TRUE;
      g_with_external_clock_input : boolean := TRUE;
      g_board_name : string := "cute";
      g_flash_secsz_kb : integer := 256; -- default for N25Q128
      g_flash_secsz_kb : integer := 64; -- default for N25Q128
      g_flash_sdbfs_baddr : integer := 16#760000#; -- default for N25Q128
      g_phys_uart : boolean := TRUE;
      g_virtual_uart : boolean := TRUE;
      ......@@ -104,8 +104,12 @@ port(
      clk_ext_stopped_i : in std_logic := '0';
      clk_ext_rst_o : out std_logic;
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      ---------------------------------------------------------------------------
      --Timing system
      ......@@ -188,6 +192,11 @@ port(
      wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      ---------------------------------------------------------------------------
      -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
      ---------------------------------------------------------------------------
      ......@@ -232,16 +241,18 @@ port(
      ---------------------------------------------------------------------------
      -- Buttons, LEDs and PPS output
      ---------------------------------------------------------------------------
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      led_act_o : out std_logic_vector(g_num_phys-1 downto 0);
      led_link_o : out std_logic_vector(g_num_phys-1 downto 0);
      btn1_i : in std_logic := '1';
      btn2_i : in std_logic := '1';
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- Link ok indication
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      );
      ......@@ -249,6 +260,7 @@ end component xwrc_board_cute_a7;
      component wr_pll_ctrl is
      generic (
      g_project_name : string := "normal";
      g_spi_clk_freq : std_logic_vector(31 downto 0) := x"00000004");
      port (
      clk_i : in std_logic;
      ......@@ -268,21 +280,31 @@ port (
      done_o : out std_logic);
      end component wr_pll_ctrl;
      component wr_fdelay_ctrl is
      component xwr_sma_config is
      generic (
      fdelay_ch0 : std_logic_vector(8 downto 0) := (others=>'0');
      fdelay_ch1 : std_logic_vector(8 downto 0) := (others=>'0'));
      g_interface_mode : t_wishbone_interface_mode := PIPELINED;
      g_address_granularity : t_wishbone_address_granularity := WORD
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      clk_serdes_i : in std_logic;
      pps_csync_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_tai_i : in std_logic_vector(39 downto 0);
      sync_data_o_p : out std_logic_vector(1 downto 0);
      sync_data_o_n : out std_logic_vector(1 downto 0);
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end component wr_fdelay_ctrl;
      fdly_en_o : out std_logic;
      fdly_sload_o : out std_logic;
      fdly_sdin_o : out std_logic;
      fdly_sclk_o : out std_logic;
      slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
      slave_o : out t_wishbone_slave_out
      );
      end component;
      constant c_null_sdb : t_sdb_device := (
      abi_class => x"0000", -- undocumented device
      ......@@ -300,5 +322,20 @@ constant c_null_sdb : t_sdb_device := (
      date => x"20201119",
      name => "WR-NULL ")));
      constant c_sma_config_sdb : t_sdb_device := (
      abi_class => x"0000", -- undocumented device
      abi_ver_major => x"01",
      abi_ver_minor => x"01",
      wbd_endian => c_sdb_endian_big,
      wbd_width => x"7", -- 8/16/32-bit port granularity
      sdb_component => (
      addr_first => x"0000000000000000",
      addr_last => x"00000000000000ff",
      product => (
      vendor_id => x"0000000000746875", -- THU
      device_id => x"736d6101",
      version => x"00000001",
      date => x"20210606",
      name => "WR-SMA-Config ")));
      end wr_cute_a7_pkg;
      board/cute_a7/wr_pll_ctrl.vhd
      View file @ 50d6bf22
      ......@@ -8,6 +8,7 @@ use work.wr_pll_ctrl_pkg.all;
      entity wr_pll_ctrl is
      generic (
      g_project_name : string := "NORMAL";
      -- clk_spi = clk/(div+1)/2 --> 6.25MHz sclk for 62.5 input (up to 25MHz)
      g_spi_clk_freq : std_logic_vector(31 downto 0) := x"00000004"
      );
      ......
      board/cute_a7/wr_pll_ctrl_pkg.vhd
      View file @ 50d6bf22
      ......@@ -6,6 +6,7 @@ package wr_pll_ctrl_pkg is
      type t_data_array is array(natural range<>) of std_logic_vector(7 downto 0);
      type t_addr_array is array(natural range<>) of std_logic_vector(15 downto 0);
      -- AD9516 settings for NORMAL
      constant c_spi_addr_array : t_addr_array :=(
      x"0000",x"0001",x"0002",x"0003",x"0004",x"0010",x"0011",x"0012",x"0013",x"0014",x"0015",x"0016",x"0017",x"0018",x"0019",x"001A",
      x"001B",x"001C",x"001D",x"001E",x"001F",x"00A0",x"00A1",x"00A2",x"00A3",x"00A4",x"00A5",x"00A6",x"00A7",x"00A8",x"00A9",x"00AA",
      ......@@ -18,7 +19,7 @@ package wr_pll_ctrl_pkg is
      x"99" ,x"00" ,x"10" ,x"C3" ,x"00" ,x"7C" ,x"05" ,x"00" ,x"0C" ,x"12" ,x"00" ,x"05" ,x"88" ,x"07" ,x"00" ,x"00",
      x"00" ,x"02" ,x"00" ,x"00" ,x"0E" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00" ,x"00" ,x"01" ,x"00",
      x"00" ,x"0A" ,x"0A" ,x"08" ,x"08" ,x"0A" ,x"0A" ,x"42" ,x"42" ,x"42" ,x"42" ,x"00" ,x"08" ,x"00" ,x"00" ,x"80",
      x"00" ,x"00" ,x"80" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"01",
      x"00" ,x"00" ,x"80" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"11" ,x"00" ,x"00" ,x"20" ,x"00" ,x"00" ,x"01",
      x"02" ,x"00" ,x"00" ,x"01"
      );
      ......
      board/cute_a7/xwrc_board_cute_a7.vhd
      View file @ 50d6bf22
      ......@@ -58,14 +58,14 @@ entity xwrc_board_cute_a7 is
      g_verbose : boolean := TRUE;
      g_with_external_clock_input : boolean := TRUE;
      g_board_name : string := "cute";
      g_flash_secsz_kb : integer := 256; -- default for N25Q128
      g_flash_secsz_kb : integer := 64; -- default for N25Q128
      g_flash_sdbfs_baddr : integer := 16#760000#; -- default for N25Q128
      g_phys_uart : boolean := TRUE;
      g_virtual_uart : boolean := TRUE;
      g_aux_clks : integer := 0;
      g_ep_rxbuf_size : integer := 1024;
      g_tx_runt_padding : boolean := TRUE;
      g_dpram_initf : string := "wrc_phy16.bram";
      g_dpram_initf : string := "";
      g_dpram_size : integer := 131072/4;
      g_interface_mode : t_wishbone_interface_mode := PIPELINED;
      g_address_granularity : t_wishbone_address_granularity := BYTE;
      ......@@ -107,15 +107,20 @@ entity xwrc_board_cute_a7 is
      clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
      -- External 10 MHz reference (cesium, GPSDO, etc.), used in Grandmaster mode
      clk_ext_i : in std_logic := '0';
      clk_ext_i : in std_logic := '0';
      clk_ext_mul_i : in std_logic := '0';
      clk_ext_mul_locked_i : in std_logic := '1';
      clk_ext_stopped_i : in std_logic := '0';
      clk_ext_rst_o : out std_logic;
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic;
      ext_tai_i : in std_logic_vector(39 downto 0);
      ext_tai_ready_i : in std_logic;
      rst_n_i : in std_logic;
      ---------------------------------------------------------------------------
      ......@@ -129,10 +134,10 @@ entity xwrc_board_cute_a7 is
      ---------------------------------------------------------------------------
      -- PHY I/f
      ---------------------------------------------------------------------------
      phy8_o : out t_phy_8bits_from_wrc_array(g_num_phys-1 downto 0);
      phy8_i : in t_phy_8bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy8_to_wrc);
      phy16_o : out t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      phy16_i : in t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy16_to_wrc);
      phy8_o : out t_phy_8bits_from_wrc_array(g_num_phys-1 downto 0);
      phy8_i : in t_phy_8bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy8_to_wrc);
      phy16_o : out t_phy_16bits_from_wrc_array(g_num_phys-1 downto 0);
      phy16_i : in t_phy_16bits_to_wrc_array(g_num_phys-1 downto 0):=(others=>c_dummy_phy16_to_wrc);
      ---------------------------------------------------------------------------
      -- I2C EEPROM
      ......@@ -145,12 +150,12 @@ entity xwrc_board_cute_a7 is
      ---------------------------------------------------------------------------
      -- SFP management info
      ---------------------------------------------------------------------------
      sfp_scl_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_scl_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      sfp_sda_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_sda_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      sfp_det_i : in std_logic_vector(g_num_phys-1 downto 0):=(others=> '1');
      -- Flash
      sfp_scl_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_scl_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      sfp_sda_o : out std_logic_vector(g_num_phys-1 downto 0);
      sfp_sda_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      sfp_det_i : in std_logic_vector(g_num_phys-1 downto 0):= (others=>'1');
      flash_spi_sclk_o : out std_logic;
      flash_spi_ncs_o : out std_logic;
      flash_spi_mosi_o : out std_logic;
      ......@@ -206,6 +211,11 @@ entity xwrc_board_cute_a7 is
      wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      eb_wrf_src_o : out t_wrf_source_out_array(g_num_phys-1 downto 0);
      eb_wrf_src_i : in t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      eb_wrf_snk_o : out t_wrf_sink_out_array(g_num_phys-1 downto 0);
      eb_wrf_snk_i : in t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      ---------------------------------------------------------------------------
      -- Etherbone WB master interface (when g_fabric_iface = ETHERBONE)
      ---------------------------------------------------------------------------
      ......@@ -262,10 +272,12 @@ entity xwrc_board_cute_a7 is
      btn2_i : in std_logic := '1';
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p: out std_logic;
      sync_clk_10m_o_n: out std_logic;
      -- Link ok indication
      link_ok_o : out std_logic_vector(g_num_phys-1 downto 0)
      );
      ......@@ -282,7 +294,7 @@ architecture struct of xwrc_board_cute_a7 is
      g_mtu : natural := 1500);
      port(
      clk_i : in std_logic;
      nRst_i : in std_logic;
      nrst_i : in std_logic;
      snk_i : in t_wrf_sink_in;
      snk_o : out t_wrf_sink_out;
      src_o : out t_wrf_source_out;
      ......@@ -311,9 +323,9 @@ architecture struct of xwrc_board_cute_a7 is
      -- WR fabric interface
      signal wrf_src_out : t_wrf_source_out_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0);
      signal wrf_src_in : t_wrf_source_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_src_in);
      signal wrf_snk_out : t_wrf_sink_out_array(g_num_phys-1 downto 0);
      signal wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0);
      signal wrf_snk_in : t_wrf_sink_in_array(g_num_phys-1 downto 0):=(others=>c_dummy_snk_in);
      -- Aux WB interface
      signal aux_master_out : t_wishbone_master_out;
      ......@@ -350,6 +362,10 @@ architecture struct of xwrc_board_cute_a7 is
      -- link state
      signal link_ok : std_logic_vector(g_num_phys-1 downto 0);
      signal pps_valid : std_logic;
      signal pps_csync : std_logic;
      signal pps_unmask : std_logic;
      signal flash_spi_sclk : std_logic;
      begin -- architecture struct
      ......@@ -412,8 +428,12 @@ begin -- architecture struct
      clk_ext_mul_locked_i => clk_ext_mul_locked_i,
      clk_ext_stopped_i => clk_ext_stopped_i,
      clk_ext_rst_o => clk_ext_rst_o,
      pps_ext_i => pps_i,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      rst_n_i => rst_n_i,
      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
      dac_hpll_data_o => dac_hpll_data_o,
      ......@@ -488,16 +508,21 @@ begin -- architecture struct
      tm_time_valid_o => tm_time_valid,
      tm_tai_o => tm_tai,
      tm_cycles_o => tm_cycles,
      pps_csync_o => pps_csync_o,
      pps_p_o => pps_o,
      pps_csync_o => pps_csync,
      pps_valid_o => pps_valid,
      pps_unmask_o => pps_unmask,
      pps_p_o => pps_p_o,
      pps_led_o => pps_led_o,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      sync_clk_10m_o_p => sync_clk_10m_o_p,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      rst_aux_n_o => aux_rst_n,
      aux_diag_i => aux_diag_in,
      aux_diag_o => aux_diag_out,
      link_ok_o => link_ok);
      pps_csync_o <= pps_csync;
      pps_valid_o <= pps_valid;
      pps_unmask_o <= pps_unmask;
      rst_aux_n_o <= aux_rst_n;
      link_ok_o <= link_ok;
      tm_time_valid_o <= tm_time_valid;
      ......@@ -525,10 +550,10 @@ begin -- architecture struct
      cmp_eb_ethernet_slave : eb_ethernet_slave
      generic map (
      g_sdb_address => x"0000000000020e00")
      g_sdb_address => x"0000000000030000")
      port map (
      clk_i => clk_sys_i,
      nRst_i => aux_rst_n,
      nrst_i => aux_rst_n,
      src_o => eb_wrf_snk_in(0),
      src_i => eb_wrf_snk_out(0),
      snk_o => eb_wrf_src_in(0),
      ......@@ -562,6 +587,12 @@ begin -- architecture struct
      wrf_src_in <= wrf_src_i;
      wrf_snk_in <= wrf_snk_i;
      eb_wrf_src_o <= eb_wrf_src_out;
      eb_wrf_snk_o <= eb_wrf_snk_out;
      eb_wrf_src_in <= eb_wrf_src_i;
      eb_wrf_snk_in <= eb_wrf_snk_i;
      aux_master_in <= aux_master_i;
      aux_master_o <= aux_master_out;
      ......
      general-cores @ 8649d40d
      Subproject commit f73bc3d2959bdaab52adf910d99ed90cabab11ab
      Subproject commit 8649d40d622bb62ae68580ad57f858920a018c1a
      vme64x-core @ 78cac871
      Subproject commit 78cac8713658de449dcccbce5a5d35131461fc34
      modules/fabric/xwrf_mux.vhd
      View file @ 50d6bf22
      ......@@ -117,7 +117,7 @@ architecture behaviour of xwrf_mux is
      signal dmux_sel : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_status_reg : std_logic_vector(15 downto 0);
      signal dmux_select : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_others : std_logic_vector(g_muxed_ports-1 downto 0);
      -- signal dmux_others : std_logic_vector(g_muxed_ports-1 downto 0);
      signal dmux_sel_zero : std_logic;
      signal dmux_snd_stat : std_logic_vector(g_muxed_ports-1 downto 0);
      signal ep_stall_mask : std_logic;
      ......@@ -206,10 +206,10 @@ begin
      demux <= DMUX_WAIT;
      else
      case demux is
      ---------------------------------------------------------------
      --State DMUX_WAIT: Wait for the WRF cycle to start and then
      -- wait for the STATUS word
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_WAIT: Wait for the WRF cycle to start and then
      -- wait for the STATUS word
      ---------------------------------------------------------------
      when DMUX_WAIT =>
      dmux_select <= (others => '0');
      dmux_snd_stat <= (others => '0');
      ......@@ -221,9 +221,9 @@ begin
      demux <= DMUX_STATUS;
      end if;
      ---------------------------------------------------------------
      --State DMUX_STATUS: Send Status word to appropriate interface
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_STATUS: Send Status word to appropriate interface
      ---------------------------------------------------------------
      when DMUX_STATUS =>
      ep_stall_mask <= '1';
      ......@@ -240,10 +240,10 @@ begin
      demux <= DMUX_PAYLOAD;
      end if;
      ---------------------------------------------------------------
      --State DMUX_PAYLOAD: Just wait here till the end of the
      -- current transfer
      ---------------------------------------------------------------
      ---------------------------------------------------------------
      --State DMUX_PAYLOAD: Just wait here till the end of the
      -- current transfer
      ---------------------------------------------------------------
      when DMUX_PAYLOAD =>
      dmux_snd_stat <= (others => '0');
      ep_stall_mask <= '0';
      ......@@ -264,27 +264,26 @@ begin
      -- dmux_others signal says for given interface I if any other interface was
      -- also matched to packet class
      dmux_others(0) <= '0';
      GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
      dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
      end generate;
      -- dmux_others(0) <= '0';
      -- GEN_DMUX_OTHERS : for I in 1 to g_muxed_ports-1 generate
      -- dmux_others(I) <= or_reduce(dmux_select(I-1 downto 0));
      -- end generate;
      -- Modify the MUX to support multi output by hm
      GEN_DMUX_CONN : for I in 0 to g_muxed_ports-1 generate
      mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).cyc <= ep_snk_i.cyc when(dmux_select(I) = '1') else
      '0';
      mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.stb when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).stb <= '1' when(dmux_snd_stat(I) = '1') else
      ep_snk_i.stb when(dmux_select(I) = '1') else
      '0';
      mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.adr when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      (others => '0');
      mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.dat when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      mux_src_o(I).adr <= c_WRF_STATUS when(dmux_snd_stat(I) = '1') else
      ep_snk_i.adr when(dmux_select(I) = '1') else
      (others => '0');
      mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1' and dmux_others(I) = '0') else
      ep_snk_i.sel when(dmux_select(I) = '1' and dmux_others(I) = '0') else
      (others => '1');
      mux_src_o(I).dat <= dmux_status_reg when(dmux_snd_stat(I) = '1') else
      ep_snk_i.dat;
      mux_src_o(I).sel <= (others => '1') when(dmux_snd_stat(I) = '1') else
      ep_snk_i.sel;
      mux_src_o(I).we <= '1';
      end generate;
      ......
      modules/wr_endpoint/ep_1000basex_pcs.vhd
      View file @ 50d6bf22
      ......@@ -433,8 +433,8 @@ begin -- rtl
      mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
      -- keep PHY reset also when SFP reports LOS (DL)
      serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown
      ;
      -- serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown or serdes_sfp_los_i;
      serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown;
      U_MDIO_WB : ep_pcs_tbi_mdio_wb
      port map (
      ......
      modules/wr_gen_10mhz/xwr_gen_10mhz.vhd
      View file @ 50d6bf22
      ......@@ -59,8 +59,8 @@ port (
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- can be wired to IODelay component in top module for precise 1-PPS
      -- alignment with clk_aux
      ......@@ -310,8 +310,8 @@ begin
      IO_RESET => rst_oserdes
      );
      sync_data_p_o <= sd_out_p(0);
      sync_data_n_o <= sd_out_n(0);
      sync_clk_10m_o_p <= sd_out_p(0);
      sync_clk_10m_o_n <= sd_out_n(0);
      wb_regs_in.pps_ior_tap_cur_i <= ppsdel_tap_i;
      ppsdel_tap_o <= wb_regs_out.pps_ior_tap_set_o;
      ppsdel_tap_wr_o <= wb_regs_out.pps_ior_tap_set_wr_o;
      ......
      modules/wr_pps_gen/pps_gen_regs.h
      View file @ 50d6bf22
      ......@@ -3,7 +3,7 @@
      * File : pps_gen_regs.h
      * Author : auto-generated by wbgen2 from pps_gen_wb.wb
      * Created : Wed Jun 5 16:28:58 2019
      * Created : Sun Mar 5 18:23:51 2023
      * Standard : ANSI C
      THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
      ......@@ -14,7 +14,11 @@
      #ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
      #define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
      #ifdef __KERNEL__
      #include <linux/types.h>
      #else
      #include <inttypes.h>
      #endif
      #if defined( __GNUC__)
      #define PACKED __attribute__ ((packed))
      ......@@ -24,7 +28,7 @@
      #ifndef __WBGEN2_MACROS_DEFINED__
      #define __WBGEN2_MACROS_DEFINED__
      #define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
      #define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
      #define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
      #define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
      #define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
      ......@@ -86,6 +90,19 @@
      /* definitions for field: Enable PPS_IN 50Ohm termination in reg: External sync control register */
      #define PPSG_ESCR_PPS_IN_TERM WBGEN2_GEN_MASK(6, 1)
      /* definitions for field: Enable TOD IN 5OOhm termination in reg: External sync control register */
      #define PPSG_ESCR_TOD_IN_TERM WBGEN2_GEN_MASK(7, 1)
      /* definitions for field: Set UTC counter to External UTC Input in reg: External sync control register */
      #define PPSG_ESCR_EXT_UTC_SYNC WBGEN2_GEN_MASK(8, 1)
      /* definitions for field: External UTC Status in reg: External sync control register */
      #define PPSG_ESCR_EXT_UTC_READY WBGEN2_GEN_MASK(9, 1)
      /* definitions for register: EXT UTC Counter register (least-significant part) */
      /* definitions for register: EXT UTC Counter register (most-significant part) */
      PACKED struct PPSG_WB {
      /* [0x0]: REG Control Register */
      uint32_t CR;
      ......@@ -103,11 +120,10 @@ PACKED struct PPSG_WB {
      uint32_t ADJ_UTCHI;
      /* [0x1c]: REG External sync control register */
      uint32_t ESCR;
      /* [0x20]: REG EXT UTC Counter register (least-significant part) */
      uint32_t EXT_CNTR_UTCLO;
      /* [0x24]: REG EXT UTC Counter register (most-significant part) */
      uint32_t EXT_CNTR_UTCHI;
      };
      #define PPSG_PERIPH_PREFIX "ppsg"
      #define PPSG_PERIPH_NAME "WR Switch PPS generator and RTC"
      #define PPSG_PERIPH_DESC WBGEN2_DESC("Unit generating PPS signals and acting as a UTC real-time clock")
      #endif
      modules/wr_pps_gen/pps_gen_wb.vhd
      View file @ 50d6bf22
      This diff is collapsed.
      modules/wr_pps_gen/pps_gen_wb.wb
      View file @ 50d6bf22
      ......@@ -232,5 +232,69 @@ peripheral {
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "Enable TOD IN 5OOhm termination";
      description = "write 1: enable 50ohm termination for TOD input \
      write 0: disable 50ohm termination for TOD input \
      read 1: 50ohm termination for TOD input enabled \
      read 0: 50ohm termination for TOD input disabled";
      prefix = "TOD_IN_TERM";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "Set UTC counter to External UTC Input";
      description = "write 1: enable UTC counter to sync to External UTC Input.\
      write 0: disable UTC counter to sync to External UTC Input";
      prefix = "EXT_TAI_SYNC";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      };
      field {
      name = "External UTC Status";
      description = "read 1: External UTC is ready.\
      read 0: External UTC is not ready";
      prefix = "EXT_TAI_READY";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      };
      };
      reg {
      name = "EXT UTC Counter register (least-significant part)";
      description = "Lower 32 bits of current UTC time";
      prefix = "EXT_CNTR_UTCLO";
      field {
      name = "UTC Counter";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "refclk_i";
      };
      };
      reg {
      name = "EXT UTC Counter register (most-significant part)";
      description = "Highest 8 bits of current UTC time";
      prefix = "EXT_CNTR_UTCHI";
      field {
      name = "UTC Counter";
      type = SLV;
      size = 8;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
      clock = "refclk_i";
      };
      };
      };
      modules/wr_pps_gen/wr_pps_gen.vhd
      View file @ 50d6bf22
      ......@@ -62,7 +62,7 @@ entity wr_pps_gen is
      rst_ref_n_i : in std_logic;
      rst_sys_n_i : in std_logic;
      wb_adr_i : in std_logic_vector(4 downto 0);
      wb_adr_i : in std_logic_vector(5 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -83,11 +83,18 @@ entity wr_pps_gen is
      ppsin_term_o : out std_logic;
      -- Single-pulse PPS output for synchronizing endpoints to
      pps_valid_int_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      ......@@ -105,7 +112,7 @@ architecture behavioral of wr_pps_gen is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(2 downto 0);
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -139,7 +146,12 @@ architecture behavioral of wr_pps_gen is
      ppsg_escr_sec_set_o : out std_logic;
      ppsg_escr_nsec_set_o : out std_logic;
      ppsg_escr_pps_unmask_o : out std_logic;
      ppsg_escr_pps_in_term_o: out std_logic);
      ppsg_escr_pps_in_term_o: out std_logic;
      ppsg_escr_tod_in_term_o : out std_logic;
      ppsg_escr_ext_tai_sync_o : out std_logic;
      ppsg_escr_ext_tai_ready_i: in std_logic;
      ppsg_ext_cntr_utclo_i : in std_logic_vector(31 downto 0);
      ppsg_ext_cntr_utchi_i : in std_logic_vector(7 downto 0));
      end component pps_gen_wb;
      -- Wisbone slave signals
      ......@@ -206,13 +218,18 @@ architecture behavioral of wr_pps_gen is
      signal pps_out_int : std_logic;
      signal pps_in_refclk : std_logic;
      signal set_ext_tai : std_logic;
      signal ext_tai : unsigned(39 downto 0);
      signal ppsg_escr_ext_tai_sync : std_logic;
      signal ppsg_escr_ext_tai_ready : std_logic;
      signal ppsg_ext_cntr_utclo : std_logic_vector(31 downto 0);
      signal ppsg_ext_cntr_utchi : std_logic_vector(7 downto 0);
      begin -- behavioral
      resized_addr(4 downto 0) <= wb_adr_i;
      resized_addr(c_wishbone_address_width-1 downto 5) <= (others => '0');
      resized_addr(5 downto 0) <= wb_adr_i;
      resized_addr(c_wishbone_address_width-1 downto 6) <= (others => '0');
      U_Adapter : wb_slave_adapter
      generic map (
      ......@@ -399,7 +416,9 @@ begin -- behavioral
      adjust_in_progress_utc <= '0';
      elsif(ppsg_cr_cnt_en = '1') then
      if(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
      if(set_ext_tai = '1') then
      cntr_utc <= ext_tai;
      elsif(ppsg_cr_cnt_set_p = '1' or ppsg_escr_sec_set = '1') then
      cntr_utc <= adj_utc;
      elsif(cntr_adjust_p = '1') then
      adjust_in_progress_utc <= '1';
      ......@@ -465,7 +484,7 @@ begin -- behavioral
      port map (
      rst_n_i => rst_n_i,
      clk_sys_i => clk_sys_i,
      wb_adr_i => wb_in.adr(2 downto 0),
      wb_adr_i => wb_in.adr(3 downto 0),
      wb_dat_i => wb_in.dat,
      wb_dat_o => wb_out.dat,
      wb_cyc_i => wb_in.cyc,
      ......@@ -498,7 +517,12 @@ begin -- behavioral
      ppsg_escr_sec_set_o => ppsg_escr_sec_set,
      ppsg_escr_nsec_set_o => ppsg_escr_nsec_set,
      ppsg_escr_pps_unmask_o => ppsg_escr_pps_unmask,
      ppsg_escr_pps_in_term_o=> ppsin_term_o);
      ppsg_escr_pps_in_term_o=> ppsin_term_o,
      ppsg_escr_tod_in_term_o => todin_term_o,
      ppsg_escr_ext_tai_sync_o => ppsg_escr_ext_tai_sync,
      ppsg_escr_ext_tai_ready_i => ppsg_escr_ext_tai_ready,
      ppsg_ext_cntr_utclo_i => ppsg_ext_cntr_utclo,
      ppsg_ext_cntr_utchi_i => ppsg_ext_cntr_utchi);
      -- drive unused signals
      wb_out.rty <= '0';
      ......@@ -511,10 +535,63 @@ begin -- behavioral
      -- drive the readout value of CNT_ADJ to 1 when the adjustment is over
      ppsg_cr_cnt_adj_i <= pps_valid_int;
      pps_valid_o <= pps_valid_int;
      pps_valid_int_o <= pps_valid_int;
      pps_valid_o <= ppsg_escr_pps_valid;
      tm_utc_o <= std_logic_vector(cntr_utc);
      tm_cycles_o <= std_logic_vector(cntr_nsec);
      tm_time_valid_o <= ppsg_escr_tm_valid;
      pps_unmask_o <= ppsg_escr_pps_unmask;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_escr_ext_tai_ready <= '0';
      elsif(set_ext_tai = '1')then
      ppsg_escr_ext_tai_ready <= '1';
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_ext_cntr_utclo <= (others => '0');
      elsif(ext_tai_valid_p_i = '1') then
      ppsg_ext_cntr_utclo <= ext_tai_i(31 downto 0);
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_ref_n_i = '0' then
      ppsg_ext_cntr_utchi <= (others => '0');
      elsif(ext_tai_valid_p_i = '1') then
      ppsg_ext_cntr_utchi <= ext_tai_i(39 downto 32);
      end if;
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      ext_tai <= unsigned(ext_tai_i);
      end if;
      end process;
      process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if((ext_tai_valid_p_i = '1') and (ext_tai_ready_i = '1') and (ppsg_escr_ext_tai_sync = '1')) then
      set_ext_tai <= '1';
      else
      set_ext_tai <= '0';
      end if;
      end if;
      end process;
      end behavioral;
      modules/wr_pps_gen/xwr_pps_gen.vhd
      View file @ 50d6bf22
      ......@@ -71,10 +71,17 @@ entity xwr_pps_gen is
      -- Single-pulse PPS output for synchronizing endpoints to
      pps_csync_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      ......@@ -98,7 +105,7 @@ architecture behavioral of xwr_pps_gen is
      clk_sys_i : in std_logic;
      rst_ref_n_i : in std_logic;
      rst_sys_n_i : in std_logic;
      wb_adr_i : in std_logic_vector(4 downto 0);
      wb_adr_i : in std_logic_vector(5 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      ......@@ -114,6 +121,12 @@ architecture behavioral of xwr_pps_gen is
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      tm_time_valid_o : out std_logic
      ......@@ -136,7 +149,7 @@ begin -- behavioral
      clk_sys_i => clk_sys_i,
      rst_ref_n_i => rst_ref_n_i,
      rst_sys_n_i => rst_sys_n_i,
      wb_adr_i => slave_i.adr(4 downto 0),
      wb_adr_i => slave_i.adr(5 downto 0),
      wb_dat_i => slave_i.dat,
      wb_dat_o => slave_o.dat,
      wb_cyc_i => slave_i.cyc,
      ......@@ -149,9 +162,15 @@ begin -- behavioral
      pps_in_i => pps_in_i,
      ppsin_term_o => ppsin_term_o,
      pps_csync_o => pps_csync_o,
      pps_valid_int_o => pps_valid_int_o,
      pps_out_o => pps_out_o,
      pps_led_o => pps_led_o,
      pps_valid_o => pps_valid_o,
      pps_unmask_o => pps_unmask_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      tm_utc_o => tm_utc_o,
      tm_cycles_o => tm_cycles_o,
      tm_time_valid_o => tm_time_valid_o
      ......
      modules/wr_sma_config/build_wb.sh 0 → 100755
      View file @ 50d6bf22
      #!/bin/bash
      mkdir -p doc
      /home/fpga/workspace/wr-tool/wishbone-gen/wbgen2 -D ./doc/sma_config.html -C sma_config_regs.h -V sma_config_wb_slave.vhd -p sma_config_wbgen2_pkg.vhd --cstyle struct --lang vhdl -H record sma_config.wb
      board/cute_a7/wr_fdelay_ctrl.vhd → modules/wr_sma_config/fine_delay_ctrl.vhd
      View file @ 50d6bf22
      ......@@ -2,37 +2,51 @@ library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      entity wr_fdelay_ctrl is
      library work;
      use work.gencores_pkg.all;
      use work.wishbone_pkg.all;
      entity fine_delay_ctrl is
      generic (
      fdelay_ch0 : std_logic_vector(8 downto 0) := (others=>'0');
      fdelay_ch1 : std_logic_vector(8 downto 0) := (others=>'0'));
      g_project_name : string := "NORMAL"
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      fine_dly_req_i : in std_logic;
      fine_dly_sel_i : in std_logic;
      fine_dly_values_i : in std_logic_vector(8 downto 0);
      fine_dly_busy_o : out std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end wr_fdelay_ctrl;
      end fine_delay_ctrl;
      architecture struct of wr_fdelay_ctrl is
      architecture struct of fine_delay_ctrl is
      constant c_fdelay_ch0 : std_logic_vector(8 downto 0) :="000001010";
      constant c_fdelay_ch1 : std_logic_vector(8 downto 0) :=(others=>'0');
      type fdly_ctrl_state is (S_IDLE, S_START_CONF_CH0, S_CONFIG_CH0, S_SPI_TRANS_CHO, S_CONFIG_DONE_CH0, S_FINISH_CH0, S_START_CONF_CH1, S_CONFIG_CH1, S_SPI_TRANS_CH1, S_CONFIG_DONE_CH1, S_FINISH_CH1);
      type fdly_ctrl_state is (S_IDLE,S_CONFIG_EN,S_SPI_LOAD,S_SPI_TRANS,S_SPI_END);
      signal delay_en : std_logic;
      signal delay_sload : std_logic;
      signal delay_sdin : std_logic;
      signal delay_sclk : std_logic;
      signal fine_dly_busy : std_logic;
      signal channel_sel : std_logic:='0';
      signal fine_dly : std_logic_vector(8 downto 0):=(others=>'0');
      signal spi_data : std_logic_vector(10 downto 0):=(others=>'0');
      begin
      signal delay_en :std_logic;
      signal delay_sload :std_logic;
      signal delay_sdin :std_logic;
      signal delay_sclk :std_logic;
      signal spi_data : std_logic_vector(10 downto 0):=(others=>'0');
      delay_en_o <= delay_en;
      delay_sload_o <= delay_sload;
      delay_sdin_o <= delay_sdin;
      delay_sclk_o <= delay_sclk;
      fine_dly_busy_o <= fine_dly_busy;
      begin
      P_FINE_DELAY_SPI: process(clk_sys_i)
      variable state : fdly_ctrl_state := S_IDLE;
      variable spi_cnt: natural range 0 to 12;
      ......@@ -40,83 +54,58 @@ begin
      if rising_edge(clk_sys_i) then
      if (rst_sys_n_i='0') then
      spi_data <= (others=>'0');
      delay_en <= '0';
      channel_sel <= '0';
      delay_sload <= '0';
      delay_sdin <= '0';
      delay_sclk <= '0';
      delay_en <= '0';
      fine_dly_busy <= '0';
      spi_cnt := 0;
      state := S_IDLE;
      else
      case(state) is
      when S_IDLE =>
      spi_data <= (others=>'0');
      delay_en <= '0';
      delay_sload <= '0';
      delay_sdin <= '0';
      delay_sclk <= '0';
      spi_cnt := 0;
      state := S_START_CONF_CH0;
      when S_START_CONF_CH0 =>
      delay_en <= '1';
      spi_data <= c_fdelay_ch0 & '0' & '0';
      state := S_CONFIG_CH0;
      when S_CONFIG_CH0 =>
      delay_sdin <= spi_data(0);
      delay_sclk <= '0';
      state := S_SPI_TRANS_CHO;
      if(spi_cnt = 11) then
      delay_sload <= '1';
      state := S_CONFIG_DONE_CH0;
      end if;
      when S_SPI_TRANS_CHO =>
      spi_data <= '0' & spi_data(10 downto 1);
      delay_sclk <= '1';
      spi_cnt := spi_cnt + 1;
      state := S_CONFIG_CH0;
      when S_CONFIG_DONE_CH0 =>
      channel_sel <= '0';
      fine_dly <= (others=>'0');
      spi_data <= (others=>'0');
      delay_en <= '0';
      delay_sload <= '0';
      spi_data <= fdelay_ch1 & '0' & '1';
      delay_sdin <= '0';
      delay_sclk <= '0';
      fine_dly_busy <= '0';
      spi_cnt := 0;
      state := S_FINISH_CH0;
      when S_FINISH_CH0 =>
      delay_en <= '0';
      state := S_START_CONF_CH1;
      if (fine_dly_req_i='1') then
      fine_dly <= fine_dly_values_i;
      channel_sel <= fine_dly_sel_i;
      fine_dly_busy <= '1';
      state := S_CONFIG_EN;
      end if;
      when S_START_CONF_CH1 =>
      delay_en <= '1';
      spi_data <= c_fdelay_ch1 & '0' & '1';
      state := S_CONFIG_CH1;
      when S_CONFIG_EN =>
      spi_data <= fine_dly & '0' & channel_sel;
      delay_en <= '1';
      state := S_SPI_LOAD;
      when S_CONFIG_CH1 =>
      when S_SPI_LOAD =>
      delay_sdin <= spi_data(0);
      delay_sclk <= '0';
      state := S_SPI_TRANS_CH1;
      state := S_SPI_TRANS;
      if(spi_cnt = 11) then
      delay_sload <= '1';
      state := S_CONFIG_DONE_CH1;
      state := S_SPI_END;
      end if;
      when S_SPI_TRANS_CH1 =>
      when S_SPI_TRANS =>
      spi_data <= '0' & spi_data(10 downto 1);
      delay_sclk <= '1';
      spi_cnt := spi_cnt + 1;
      state := S_CONFIG_CH1;
      state := S_SPI_LOAD;
      when S_CONFIG_DONE_CH1 =>
      when S_SPI_END =>
      delay_sload <= '0';
      spi_data <= (others => '0');
      spi_cnt := 0;
      state := S_FINISH_CH1;
      when S_FINISH_CH1 =>
      delay_en <= '0';
      state := S_FINISH_CH1;
      delay_en <= '0';
      state := S_IDLE;
      fine_dly_busy <= '0';
      when others =>
      state := S_IDLE;
      ......@@ -125,10 +114,5 @@ begin
      end if;
      end process P_FINE_DELAY_SPI;
      delay_en_o <= delay_en;
      delay_sload_o <= delay_sload;
      delay_sdin_o <= delay_sdin;
      delay_sclk_o <= delay_sclk;
      end struct;
      modules/wr_sma_config/oserdes_8_to_1.v 0 → 100644
      View file @ 50d6bf22
      // file: selectio_wiz_0_selectio_wiz.v
      // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
      //
      // This file contains confidential and proprietary information
      // of Xilinx, Inc. and is protected under U.S. and
      // international copyright and other intellectual property
      // laws.
      //
      // DISCLAIMER
      // This disclaimer is not a license and does not grant any
      // rights to the materials distributed herewith. Except as
      // otherwise provided in a valid license issued to you by
      // Xilinx, and to the maximum extent permitted by applicable
      // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
      // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
      // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
      // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
      // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
      // (2) Xilinx shall not be liable (whether in contract or tort,
      // including negligence, or under any other theory of
      // liability) for any loss or damage of any kind or nature
      // related to, arising under or in connection with these
      // materials, including for any direct, or any indirect,
      // special, incidental, or consequential loss or damage
      // (including loss of data, profits, goodwill, or any type of
      // loss or damage suffered as a result of any action brought
      // by a third party) even if such damage or loss was
      // reasonably foreseeable or Xilinx had been advised of the
      // possibility of the same.
      //
      // CRITICAL APPLICATIONS
      // Xilinx products are not designed or intended to be fail-
      // safe, or for use in any application requiring fail-safe
      // performance, such as life-support or safety devices or
      // systems, Class III medical devices, nuclear facilities,
      // applications related to the deployment of airbags, or any
      // other applications that could lead to death, personal
      // injury, or severe property or environmental damage
      // (individually and collectively, "Critical
      // Applications"). Customer assumes the sole risk and
      // liability of any use of Xilinx products in Critical
      // Applications, subject only to applicable laws and
      // regulations governing limitations on product liability.
      //
      // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
      // PART OF THIS FILE AT ALL TIMES.
      //----------------------------------------------------------------------------
      // User entered comments
      //----------------------------------------------------------------------------
      // None
      //----------------------------------------------------------------------------
      `timescale 1ps/1ps
      module oserdes_8_to_1
      // width of the data for the system
      #(parameter SYS_W = 1,
      // width of the data for the device
      parameter DEV_W = 8)
      (
      // From the device out to the system
      input [DEV_W-1:0] data_out_from_device,
      output [SYS_W-1:0] data_out_to_pins_p,
      output [SYS_W-1:0] data_out_to_pins_n,
      input clk_in, // Fast clock input from PLL/MMCM
      input clk_div_in, // Slow clock input from PLL/MMCM
      input io_reset);
      localparam num_serial_bits = DEV_W/SYS_W;
      wire clock_enable = 1'b1;
      // Signal declarations
      ////------------------------------
      // Before the buffer
      wire [SYS_W-1:0] data_out_to_pins_int;
      // Between the delay and serdes
      wire [SYS_W-1:0] data_out_to_pins_predelay;
      // Array to use intermediately from the serdes to the internal
      // devices. bus "0" is the leftmost bus
      wire [SYS_W-1:0] oserdes_d[0:13]; // fills in starting with 13
      // Create the clock logic
      // We have multiple bits- step over every bit, instantiating the required elements
      genvar pin_count;
      genvar slice_count;
      generate for (pin_count = 0; pin_count < SYS_W; pin_count = pin_count + 1) begin: pins
      // Instantiate the buffers
      ////------------------------------
      // Instantiate a buffer for every bit of the data bus
      OBUFDS
      #(.IOSTANDARD ("LVDS_25"))
      obufds_inst
      (.O (data_out_to_pins_p [pin_count]),
      .OB (data_out_to_pins_n [pin_count]),
      .I (data_out_to_pins_int[pin_count]));
      // Pass through the delay
      ////-------------------------------
      assign data_out_to_pins_int[pin_count] = data_out_to_pins_predelay[pin_count];
      // Instantiate the serdes primitive
      ////------------------------------
      // declare the oserdes
      OSERDESE2
      # (
      .DATA_RATE_OQ ("SDR"),
      .DATA_RATE_TQ ("SDR"),
      .DATA_WIDTH (8),
      .TRISTATE_WIDTH (1),
      .SERDES_MODE ("MASTER"))
      oserdese2_master (
      .D1 (oserdes_d[13][pin_count]),
      .D2 (oserdes_d[12][pin_count]),
      .D3 (oserdes_d[11][pin_count]),
      .D4 (oserdes_d[10][pin_count]),
      .D5 (oserdes_d[9][pin_count]),
      .D6 (oserdes_d[8][pin_count]),
      .D7 (oserdes_d[7][pin_count]),
      .D8 (oserdes_d[6][pin_count]),
      .T1 (1'b0),
      .T2 (1'b0),
      .T3 (1'b0),
      .T4 (1'b0),
      .SHIFTIN1 (1'b0),
      .SHIFTIN2 (1'b0),
      .SHIFTOUT1 (),
      .SHIFTOUT2 (),
      .OCE (clock_enable),
      .CLK (clk_in),
      .CLKDIV (clk_div_in),
      .OQ (data_out_to_pins_predelay[pin_count]),
      .TQ (),
      .OFB (),
      .TFB (),
      .TBYTEIN (1'b0),
      .TBYTEOUT (),
      .TCE (1'b0),
      .RST (io_reset));
      // Concatenate the serdes outputs together. Keep the timesliced
      // bits together, and placing the earliest bits on the right
      // ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
      // the output will be 3210, 7654, ...
      ////---------------------------------------------------------
      for (slice_count = 0; slice_count < num_serial_bits; slice_count = slice_count + 1) begin: out_slices
      // This places the first data in time on the right
      assign oserdes_d[14-slice_count-1] =
      data_out_from_device[slice_count];
      // To place the first data in time on the left, use the
      // following code, instead
      // assign oserdes_d[slice_count] =
      // data_out_from_device[slice_count];
      end
      end
      endgenerate
      endmodule
      modules/wr_sma_config/sma_config.wb 0 → 100644
      View file @ 50d6bf22
      -- -*- Mode: LUA; tab-width: 2 -*-
      -- CUTE-WR-A7 SMA Output Control
      --
      -- Use wbgen2 to generate code, documentation and more.
      -- wbgen2 is available at:
      -- http://www.ohwr.org/projects/wishbone-gen
      --
      peripheral {
      name = "WR aux sma output generation module";
      description = "The module allows gerating WR-aligned signal including PPS/mPPS/\
      UTC Coding and other signal of a given frequency, duty cycle and phase. \
      The output signals of two SMA interfaces can be configured. \
      The fine delay chip can also be configured via this module.\
      The By default it is configured to generate 10MHz signal and PPS.";
      hdl_entity = "sma_config_wb";
      prefix = "sma_config";
      reg {
      name = "SMA0 MUX";
      prefix = "SMA0";
      field {
      name = "SMA0 Signal Selection";
      description = "Select the signal of SMA0.\
      0: UTC Coding\
      1: Customed Frequency.";
      prefix = "MUX";
      size = 8;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA1 MUX";
      prefix = "SMA1";
      field {
      name = "SMA1 Signal Selection";
      description = "Select the signal of SMA1.\
      0: UTC Coding\
      1: Customed Frequency.";
      prefix = "MUX";
      size = 8;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Period Register : High State";
      prefix = "CUS_PRH";
      field {
      name = "High state length";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Period Register : Low State";
      prefix = "CUS_PRL";
      field {
      name = "Low state width";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "Customed Signal Coarse Shift Register";
      prefix = "CUS_CSR";
      field {
      name = "Coarse shift value in 2ns cycles.";
      description = "MUST be not larger than the required clock period";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "PPS Period High Register";
      prefix = "PPS_PRH";
      field {
      name = "High state width";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "PPS Coarse Shift Register";
      prefix = "PPS_CSR";
      field {
      name = "Coarse shift value";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "UTC Coding Coarse Shift Register";
      prefix = "UTC_CSR";
      field {
      name = "Coarse shift value";
      description = "Defined as a number of 2ns cycles.";
      size = 29;
      type = SLV;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA0 Fine Delays Register";
      prefix = "SMA0_FDLY";
      field {
      name = "fine delay counter";
      description = "delay chip value to SMA0 signals";
      type = SLV;
      size = 9;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      reg {
      name = "SMA1 Fine Delays Register";
      prefix = "SMA1_FDLY";
      field {
      name = "fine delay counter";
      description = "delay chip value to SMA1 signals";
      type = SLV;
      size = 9;
      access_bus = READ_WRITE;
      access_dev = READ_WRITE;
      load = LOAD_EXT;
      };
      };
      }
      modules/wr_sma_config/sma_config_pkg.vhd 0 → 100644
      View file @ 50d6bf22
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      library work;
      use work.wishbone_pkg.all;
      use work.sma_config_wbgen2_pkg.all;
      package sma_config_pkg is
      constant c_DATA_W : integer := 8; -- parallel data width going to serdes
      constant c_HALF : integer := 25;-- default high/low width for 10MHz
      component sma_config_wb is
      port (
      rst_n_i : in std_logic;
      clk_sys_i : in std_logic;
      wb_adr_i : in std_logic_vector(3 downto 0);
      wb_dat_i : in std_logic_vector(31 downto 0);
      wb_dat_o : out std_logic_vector(31 downto 0);
      wb_cyc_i : in std_logic;
      wb_sel_i : in std_logic_vector(3 downto 0);
      wb_stb_i : in std_logic;
      wb_we_i : in std_logic;
      wb_ack_o : out std_logic;
      wb_stall_o : out std_logic;
      regs_i : in t_sma_config_in_registers;
      regs_o : out t_sma_config_out_registers
      );
      end component;
      component oserdes_8_to_1 is
      generic(
      sys_w : integer := 1;
      dev_w : integer := 8);
      port(
      DATA_OUT_FROM_DEVICE : in std_logic_vector(dev_w-1 downto 0);
      DATA_OUT_TO_PINS_P : out std_logic_vector(sys_w-1 downto 0);
      DATA_OUT_TO_PINS_N : out std_logic_vector(sys_w-1 downto 0);
      CLK_IN : in std_logic;
      CLK_DIV_IN : in std_logic;
      IO_RESET : in std_logic);
      end component;
      component fine_delay_ctrl is
      generic (
      g_project_name : string := "NORMAL"
      );
      port (
      rst_sys_n_i : in std_logic;
      clk_sys_i : in std_logic;
      fine_dly_req_i : in std_logic;
      fine_dly_sel_i : in std_logic;
      fine_dly_values_i : in std_logic_vector(8 downto 0);
      fine_dly_busy_o : out std_logic;
      delay_en_o : out std_logic;
      delay_sload_o : out std_logic;
      delay_sdin_o : out std_logic;
      delay_sclk_o : out std_logic
      );
      end component;
      component utc_coding is
      port(
      clk_ref_i : in std_logic;
      rst_n_i : in std_logic;
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_utc_i : in std_logic_vector(39 downto 0);
      tm_serial_o : out std_logic
      );
      end component;
      end package;
      --package body shine_config_pkg is
      --end package body;
      modules/wr_sma_config/sma_config_wb_slave.vhd 0 → 100644
      View file @ 50d6bf22
      This diff is collapsed.
      modules/wr_sma_config/sma_config_wbgen2_pkg.vhd 0 → 100644
      View file @ 50d6bf22
      ---------------------------------------------------------------------------------------
      -- Title : Wishbone slave core for WR aux sma output generation module
      ---------------------------------------------------------------------------------------
      -- File : sma_config_wbgen2_pkg.vhd
      -- Author : auto-generated by wbgen2 from sma_config.wb
      -- Created : Mon Oct 17 22:55:06 2022
      -- Standard : VHDL'87
      ---------------------------------------------------------------------------------------
      -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE sma_config.wb
      -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
      ---------------------------------------------------------------------------------------
      library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      package sma_config_wbgen2_pkg is
      -- Input registers (user design -> WB slave)
      type t_sma_config_in_registers is record
      sma0_mux_i : std_logic_vector(7 downto 0);
      sma1_mux_i : std_logic_vector(7 downto 0);
      cus_prh_i : std_logic_vector(28 downto 0);
      cus_prl_i : std_logic_vector(28 downto 0);
      cus_csr_i : std_logic_vector(28 downto 0);
      pps_prh_i : std_logic_vector(28 downto 0);
      pps_csr_i : std_logic_vector(28 downto 0);
      utc_csr_i : std_logic_vector(28 downto 0);
      sma0_fdly_i : std_logic_vector(8 downto 0);
      sma1_fdly_i : std_logic_vector(8 downto 0);
      end record;
      constant c_sma_config_in_registers_init_value: t_sma_config_in_registers := (
      sma0_mux_i => (others => '0'),
      sma1_mux_i => (others => '0'),
      cus_prh_i => (others => '0'),
      cus_prl_i => (others => '0'),
      cus_csr_i => (others => '0'),
      pps_prh_i => (others => '0'),
      pps_csr_i => (others => '0'),
      utc_csr_i => (others => '0'),
      sma0_fdly_i => (others => '0'),
      sma1_fdly_i => (others => '0')
      );
      -- Output registers (WB slave -> user design)
      type t_sma_config_out_registers is record
      sma0_mux_o : std_logic_vector(7 downto 0);
      sma0_mux_load_o : std_logic;
      sma1_mux_o : std_logic_vector(7 downto 0);
      sma1_mux_load_o : std_logic;
      cus_prh_o : std_logic_vector(28 downto 0);
      cus_prh_load_o : std_logic;
      cus_prl_o : std_logic_vector(28 downto 0);
      cus_prl_load_o : std_logic;
      cus_csr_o : std_logic_vector(28 downto 0);
      cus_csr_load_o : std_logic;
      pps_prh_o : std_logic_vector(28 downto 0);
      pps_prh_load_o : std_logic;
      pps_csr_o : std_logic_vector(28 downto 0);
      pps_csr_load_o : std_logic;
      utc_csr_o : std_logic_vector(28 downto 0);
      utc_csr_load_o : std_logic;
      sma0_fdly_o : std_logic_vector(8 downto 0);
      sma0_fdly_load_o : std_logic;
      sma1_fdly_o : std_logic_vector(8 downto 0);
      sma1_fdly_load_o : std_logic;
      end record;
      constant c_sma_config_out_registers_init_value: t_sma_config_out_registers := (
      sma0_mux_o => (others => '0'),
      sma0_mux_load_o => '0',
      sma1_mux_o => (others => '0'),
      sma1_mux_load_o => '0',
      cus_prh_o => (others => '0'),
      cus_prh_load_o => '0',
      cus_prl_o => (others => '0'),
      cus_prl_load_o => '0',
      cus_csr_o => (others => '0'),
      cus_csr_load_o => '0',
      pps_prh_o => (others => '0'),
      pps_prh_load_o => '0',
      pps_csr_o => (others => '0'),
      pps_csr_load_o => '0',
      utc_csr_o => (others => '0'),
      utc_csr_load_o => '0',
      sma0_fdly_o => (others => '0'),
      sma0_fdly_load_o => '0',
      sma1_fdly_o => (others => '0'),
      sma1_fdly_load_o => '0'
      );
      function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers;
      function f_x_to_zero (x:std_logic) return std_logic;
      function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
      end package;
      package body sma_config_wbgen2_pkg is
      function f_x_to_zero (x:std_logic) return std_logic is
      begin
      if x = '1' then
      return '1';
      else
      return '0';
      end if;
      end function;
      function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
      variable tmp: std_logic_vector(x'length-1 downto 0);
      begin
      for i in 0 to x'length-1 loop
      if(x(i) = 'X' or x(i) = 'U') then
      tmp(i):= '0';
      else
      tmp(i):=x(i);
      end if;
      end loop;
      return tmp;
      end function;
      function "or" (left, right: t_sma_config_in_registers) return t_sma_config_in_registers is
      variable tmp: t_sma_config_in_registers;
      begin
      tmp.sma0_mux_i := f_x_to_zero(left.sma0_mux_i) or f_x_to_zero(right.sma0_mux_i);
      tmp.sma1_mux_i := f_x_to_zero(left.sma1_mux_i) or f_x_to_zero(right.sma1_mux_i);
      tmp.cus_prh_i := f_x_to_zero(left.cus_prh_i) or f_x_to_zero(right.cus_prh_i);
      tmp.cus_prl_i := f_x_to_zero(left.cus_prl_i) or f_x_to_zero(right.cus_prl_i);
      tmp.cus_csr_i := f_x_to_zero(left.cus_csr_i) or f_x_to_zero(right.cus_csr_i);
      tmp.pps_prh_i := f_x_to_zero(left.pps_prh_i) or f_x_to_zero(right.pps_prh_i);
      tmp.pps_csr_i := f_x_to_zero(left.pps_csr_i) or f_x_to_zero(right.pps_csr_i);
      tmp.utc_csr_i := f_x_to_zero(left.utc_csr_i) or f_x_to_zero(right.utc_csr_i);
      tmp.sma0_fdly_i := f_x_to_zero(left.sma0_fdly_i) or f_x_to_zero(right.sma0_fdly_i);
      tmp.sma1_fdly_i := f_x_to_zero(left.sma1_fdly_i) or f_x_to_zero(right.sma1_fdly_i);
      return tmp;
      end function;
      end package body;
      modules/wr_sma_config/utc_coding.vhd 0 → 100644
      View file @ 50d6bf22
      Library ieee;
      use ieee.std_logic_1164.all;
      use ieee.numeric_std.all;
      entity utc_coding is
      port(
      clk_ref_i : in std_logic;
      rst_n_i : in std_logic;
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      tm_utc_i : in std_logic_vector(39 downto 0);
      tm_serial_o : out std_logic
      );
      end utc_coding;
      Architecture beha of utc_coding is
      type t_state is (idle, wt_utc, tx_utc);
      signal state : t_state;
      signal cnt : unsigned(5 downto 0);
      signal tm_utc_int : std_logic_vector(39 downto 0);
      begin
      p_tm_serial : process(clk_ref_i)
      begin
      if rising_edge(clk_ref_i) then
      if rst_n_i = '0' then
      tm_serial_o <= '0';
      cnt <= (others => '0');
      state <= idle;
      tm_utc_int <= (others => '0');
      else
      case state is
      when idle =>
      if (pps_i = '1' and pps_valid_i = '1') then
      tm_serial_o <= '1';
      state <= wt_utc;
      else
      tm_serial_o <= '0';
      end if;
      when wt_utc =>
      tm_serial_o <= '0';
      tm_utc_int <= tm_utc_i;
      cnt <= to_unsigned(40,6);
      state <= tx_utc;
      when tx_utc =>
      tm_serial_o <= tm_utc_int(tm_utc_int'high);
      tm_utc_int <= tm_utc_int(tm_utc_int'high-1 downto 0) & '0';
      if cnt = 0 then
      state <= idle;
      else
      cnt <= cnt -1;
      end if;
      when others => state <= idle;
      end case;
      end if;
      end if;
      end process p_tm_serial;
      end beha;
      \ No newline at end of file
      modules/wr_sma_config/xwr_sma_config.vhd 0 → 100644
      View file @ 50d6bf22
      This diff is collapsed.
      modules/wrc_core/wr_core.vhd
      View file @ 50d6bf22
      This diff is collapsed.
      modules/wrc_core/wrc_periph.vhd
      View file @ 50d6bf22
      ......@@ -509,6 +509,9 @@ begin
      generic map(
      g_with_virtual_uart => g_virtual_uart,
      g_with_physical_uart => g_phys_uart,
      g_with_physical_uart_fifo => true,
      g_tx_fifo_size => 256,
      g_rx_fifo_size => 256,
      g_interface_mode => PIPELINED,
      g_address_granularity => BYTE,
      g_vuart_fifo_size => g_vuart_fifo_size
      ......@@ -525,7 +528,6 @@ begin
      uart_rxd_i => uart_rxd_i,
      uart_txd_o => uart_txd_o
      );
      --------------------------------------
      -- 1-WIRE
      --------------------------------------
      ......
      modules/wrc_core/wrcore_pkg.vhd
      View file @ 50d6bf22
      ......@@ -86,9 +86,15 @@ package wrcore_pkg is
      pps_in_i : in std_logic;
      ppsin_term_o : out std_logic;
      pps_csync_o : out std_logic;
      pps_valid_int_o : out std_logic;
      pps_out_o : out std_logic;
      pps_led_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      tm_utc_o : out std_logic_vector(39 downto 0);
      tm_cycles_o : out std_logic_vector(27 downto 0);
      tm_time_valid_o : out std_logic
      ......@@ -406,6 +412,10 @@ package wrcore_pkg is
      clk_ext_i : in std_logic := '0';
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      dac_hpll_load_p1_o : out std_logic;
      ......@@ -521,10 +531,11 @@ package wrcore_pkg is
      tm_cycles_o : out std_logic_vector(27 downto 0);
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -602,6 +613,10 @@ package wrcore_pkg is
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      -----------------------------------------
      ......@@ -800,10 +815,11 @@ package wrcore_pkg is
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -860,8 +876,8 @@ package wrcore_pkg is
      pps_i : in std_logic;
      pps_valid_i : in std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      -- can be wired to IODelay component in top module for precise 1-PPS
      -- alignment with clk_aux
      ......
      modules/wrc_core/xwr_core.vhd
      View file @ 50d6bf22
      ......@@ -136,6 +136,10 @@ entity xwr_core is
      -- External PPS input (cesium, GPSDO, etc.), used in Grandmaster mode
      pps_ext_i : in std_logic := '0';
      ppsin_term_o : out std_logic;
      todin_term_o : out std_logic;
      ext_tai_valid_p_i : in std_logic := '0';
      ext_tai_i : in std_logic_vector(39 downto 0) := (others => '0');
      ext_tai_ready_i : in std_logic := '0';
      rst_n_i : in std_logic;
      ......@@ -299,10 +303,11 @@ entity xwr_core is
      -- 1PPS output
      pps_csync_o : out std_logic;
      pps_valid_o : out std_logic;
      pps_unmask_o : out std_logic;
      pps_p_o : out std_logic;
      pps_led_o : out std_logic;
      sync_data_p_o : out std_logic;
      sync_data_n_o : out std_logic;
      sync_clk_10m_o_p : out std_logic;
      sync_clk_10m_o_n : out std_logic;
      rst_aux_n_o : out std_logic;
      ......@@ -365,6 +370,10 @@ begin
      clk_ext_rst_o => clk_ext_rst_o,
      pps_ext_i => pps_ext_i,
      ppsin_term_o => ppsin_term_o,
      todin_term_o => todin_term_o,
      ext_tai_valid_p_i => ext_tai_valid_p_i,
      ext_tai_i => ext_tai_i,
      ext_tai_ready_i => ext_tai_ready_i,
      rst_n_i => rst_n_i,
      dac_hpll_load_p1_o => dac_hpll_load_p1_o,
      ......@@ -506,10 +515,11 @@ begin
      tm_cycles_o => tm_cycles_o,
      pps_csync_o => pps_csync_o,
      pps_valid_o => pps_valid_o,
      pps_unmask_o => pps_unmask_o,
      pps_p_o => pps_p_o,
      pps_led_o => pps_led_o,
      sync_data_p_o => sync_data_p_o,
      sync_data_n_o => sync_data_n_o,
      sync_clk_10m_o_p => sync_clk_10m_o_p,
      sync_clk_10m_o_n => sync_clk_10m_o_n,
      rst_aux_n_o => rst_aux_n_o,
      link_ok_o => link_ok_o,
      aux_diag_i => aux_diag_i,
      ......
      platform/xilinx/wr_gtp_phy/family7-gtp/wr_gtp_phy_family7.vhd
      View file @ 50d6bf22
      ......@@ -108,9 +108,11 @@ architecture structure of wr_gtp_phy_family7 is
      type state_type_array is array(integer range <>) of state_type;
      signal state : state_type_array(g_num_phys-1 downto 0);
      signal rst_synced : std_logic_vector(1 downto 0);
      signal rst_int : std_logic_vector(1 downto 0);
      signal areset : std_logic_vector(g_num_phys-1 downto 0);
      signal rst_synced : std_logic_vector(g_num_phys-1 downto 0);
      signal rst_int : std_logic_vector(g_num_phys-1 downto 0);
      signal gttxreset : std_logic_vector(g_num_phys-1 downto 0);
      signal PLL_RESET : std_logic_vector(g_num_phys-1 downto 0);
      signal clk_tx_buf : std_logic_vector(g_num_phys-1 downto 0);
      signal pll_locked : std_logic_vector(g_num_phys-1 downto 0);
      ......@@ -221,11 +223,12 @@ begin
      gen_RESET: for i in 0 to (g_num_phys-1) generate
      areset(i) <= areset_i or phy16_i(i).rst;
      -- PLL reset
      U_EdgeDet_areset_i : gc_sync_ffs port map (
      clk_i => clk_ref_i(i),
      rst_n_i => '1',
      data_i => areset_i,
      data_i => areset(i),
      ppulse_o => rst_synced(i));
      process(clk_ref_i(i), rst_synced(i))
      ......@@ -348,6 +351,10 @@ gen_GTP: for i in 0 to (g_num_phys-1) generate
      I => GT_CHANNEL_SIG_o(i).TXOUTCLK,
      O => clk_tx_buf(i));
      -- LPDC signals
      gttxreset(i) <= pll_locked_n(i) or phy16_i(i).lpc_ctrl(0);
      phy16_o(i).lpc_stat(0) <= GT_CHANNEL_SIG_o(i).TXRESETDONE;
      GT_CHANNEL_SIG_i(i).RST_IN <= '1' when state(i) = count_done else '0';
      GT_CHANNEL_SIG_i(i).DRPCLK_IN <= clk_ref_i(i);
      GT_CHANNEL_SIG_i(i).DRPDI_IN <= (others => '0');
      ......@@ -363,7 +370,7 @@ gen_GTP: for i in 0 to (g_num_phys-1) generate
      GT_CHANNEL_SIG_i(i).RXLPMHFHOLD <= '0';
      GT_CHANNEL_SIG_i(i).RXLPMLFHOLD <= '0';
      GT_CHANNEL_SIG_i(i).GTRXRESET <= gs(i).GTRXRESET;
      GT_CHANNEL_SIG_i(i).GTTXRESET <= pll_locked_n(i);
      GT_CHANNEL_SIG_i(i).GTTXRESET <= gttxreset(i);
      GT_CHANNEL_SIG_i(i).TXUSERRDY <= pll_locked(i);
      GT_CHANNEL_SIG_i(i).TXDATA(15 downto 0) <= phy16_i(i).tx_data(7 downto 0) & phy16_i(i).tx_data(15 downto 8);
      GT_CHANNEL_SIG_i(i).TXUSRCLK <= clk_tx_buf(i);
      ......
      platform/xilinx/xwrc_platform_xilinx.vhd
      View file @ 50d6bf22
      This diff is collapsed.
      sim/pps_gen_regs.v
      View file @ 50d6bf22
      `define ADDR_PPSG_CR 5'h0
      `define ADDR_PPSG_CR 6'h0
      `define PPSG_CR_CNT_RST_OFFSET 0
      `define PPSG_CR_CNT_RST 32'h00000001
      `define PPSG_CR_CNT_EN_OFFSET 1
      ......@@ -9,13 +9,13 @@
      `define PPSG_CR_CNT_SET 32'h00000008
      `define PPSG_CR_PWIDTH_OFFSET 4
      `define PPSG_CR_PWIDTH 32'hfffffff0
      `define ADDR_PPSG_CNTR_NSEC 5'h4
      `define ADDR_PPSG_CNTR_UTCLO 5'h8
      `define ADDR_PPSG_CNTR_UTCHI 5'hc
      `define ADDR_PPSG_ADJ_NSEC 5'h10
      `define ADDR_PPSG_ADJ_UTCLO 5'h14
      `define ADDR_PPSG_ADJ_UTCHI 5'h18
      `define ADDR_PPSG_ESCR 5'h1c
      `define ADDR_PPSG_CNTR_NSEC 6'h4
      `define ADDR_PPSG_CNTR_UTCLO 6'h8
      `define ADDR_PPSG_CNTR_UTCHI 6'hc
      `define ADDR_PPSG_ADJ_NSEC 6'h10
      `define ADDR_PPSG_ADJ_UTCLO 6'h14
      `define ADDR_PPSG_ADJ_UTCHI 6'h18
      `define ADDR_PPSG_ESCR 6'h1c
      `define PPSG_ESCR_SYNC_OFFSET 0
      `define PPSG_ESCR_SYNC 32'h00000001
      `define PPSG_ESCR_PPS_UNMASK_OFFSET 1
      ......@@ -30,3 +30,11 @@
      `define PPSG_ESCR_NSEC_SET 32'h00000020
      `define PPSG_ESCR_PPS_IN_TERM_OFFSET 6
      `define PPSG_ESCR_PPS_IN_TERM 32'h00000040
      `define PPSG_ESCR_TOD_IN_TERM_OFFSET 7
      `define PPSG_ESCR_TOD_IN_TERM 32'h00000080
      `define PPSG_ESCR_EXT_TAI_SYNC_OFFSET 8
      `define PPSG_ESCR_EXT_TAI_SYNC 32'h00000100
      `define PPSG_ESCR_EXT_TAI_READY_OFFSET 9
      `define PPSG_ESCR_EXT_TAI_READY 32'h00000200
      `define ADDR_PPSG_EXT_CNTR_UTCLO 6'h20
      `define ADDR_PPSG_EXT_CNTR_UTCHI 6'h24
      top/cute_a7_ref_design/cute_a7_core.vhd 0 → 100644
      View file @ 50d6bf22
      This diff is collapsed.
      top/cute_a7_ref_design/cute_a7_ref_design.mmi deleted 100644 → 0
      View file @ fecc11ee
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X0Y13">
      <DataWidth MSB="0" LSB="0"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X0Y16">
      <DataWidth MSB="1" LSB="1"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X0Y15">
      <DataWidth MSB="2" LSB="2"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X0Y11">
      <DataWidth MSB="3" LSB="3"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X0Y12">
      <DataWidth MSB="4" LSB="4"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X1Y10">
      <DataWidth MSB="5" LSB="5"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y14">
      <DataWidth MSB="6" LSB="6"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X0Y14">
      <DataWidth MSB="7" LSB="7"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X0Y3">
      <DataWidth MSB="8" LSB="8"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X1Y2">
      <DataWidth MSB="9" LSB="9"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X0Y2">
      <DataWidth MSB="10" LSB="10"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X1Y4">
      <DataWidth MSB="11" LSB="11"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X1Y3">
      <DataWidth MSB="12" LSB="12"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X0Y4">
      <DataWidth MSB="13" LSB="13"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X0Y6">
      <DataWidth MSB="14" LSB="14"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X0Y5">
      <DataWidth MSB="15" LSB="15"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X1Y7">
      <DataWidth MSB="16" LSB="16"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X0Y7">
      <DataWidth MSB="17" LSB="17"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X2Y7">
      <DataWidth MSB="18" LSB="18"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X0Y8">
      <DataWidth MSB="19" LSB="19"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X0Y9">
      <DataWidth MSB="20" LSB="20"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X1Y5">
      <DataWidth MSB="21" LSB="21"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y6">
      <DataWidth MSB="22" LSB="22"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X2Y6">
      <DataWidth MSB="23" LSB="23"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 -->
      <BitLane MemType="RAMB32" Placement="X2Y12">
      <DataWidth MSB="24" LSB="24"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 -->
      <BitLane MemType="RAMB32" Placement="X2Y13">
      <DataWidth MSB="25" LSB="25"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 -->
      <BitLane MemType="RAMB32" Placement="X1Y9">
      <DataWidth MSB="26" LSB="26"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 -->
      <BitLane MemType="RAMB32" Placement="X2Y9">
      <DataWidth MSB="27" LSB="27"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 -->
      <BitLane MemType="RAMB32" Placement="X2Y10">
      <DataWidth MSB="28" LSB="28"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 -->
      <BitLane MemType="RAMB32" Placement="X2Y8">
      <DataWidth MSB="29" LSB="29"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 -->
      <BitLane MemType="RAMB32" Placement="X1Y8">
      <DataWidth MSB="30" LSB="30"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      <!-- cmp_board_mini_a7/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 -->
      <BitLane MemType="RAMB32" Placement="X2Y11">
      <DataWidth MSB="31" LSB="31"/>
      <AddressRange Begin="0" End="32767"/>
      <Parity NumBits="0" ON="false"/>
      </BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a35tcsg325-2"/>
      </Config>
      </MemInfo>
      top/cute_a7_ref_design/cute_a7_ref_design_35t.mmi 0 → 100644
      View file @ 50d6bf22
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y14"> <DataWidth MSB="0" LSB="0"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 --><BitLane MemType="RAMB32" Placement="X1Y17"> <DataWidth MSB="1" LSB="1"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y17"> <DataWidth MSB="2" LSB="2"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 --><BitLane MemType="RAMB32" Placement="X2Y15"> <DataWidth MSB="4" LSB="4"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y14"> <DataWidth MSB="5" LSB="5"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y16"> <DataWidth MSB="6" LSB="6"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y18"> <DataWidth MSB="7" LSB="7"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y15"> <DataWidth MSB="3" LSB="3"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y5"> <DataWidth MSB="8" LSB="8"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y5"> <DataWidth MSB="9" LSB="9"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y6"> <DataWidth MSB="10" LSB="10"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y6"> <DataWidth MSB="11" LSB="11"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 --><BitLane MemType="RAMB32" Placement="X2Y7"> <DataWidth MSB="12" LSB="12"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y4"> <DataWidth MSB="13" LSB="13"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y4"> <DataWidth MSB="14" LSB="14"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y3"> <DataWidth MSB="15" LSB="15"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y10"> <DataWidth MSB="16" LSB="16"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 --><BitLane MemType="RAMB32" Placement="X0Y10"> <DataWidth MSB="17" LSB="17"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 --><BitLane MemType="RAMB32" Placement="X0Y11"> <DataWidth MSB="18" LSB="18"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 --><BitLane MemType="RAMB32" Placement="X0Y12"> <DataWidth MSB="19" LSB="19"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y7"> <DataWidth MSB="20" LSB="20"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 --><BitLane MemType="RAMB32" Placement="X0Y8"> <DataWidth MSB="21" LSB="21"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 --><BitLane MemType="RAMB32" Placement="X0Y9"> <DataWidth MSB="22" LSB="22"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 --><BitLane MemType="RAMB32" Placement="X0Y7"> <DataWidth MSB="23" LSB="23"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y13"> <DataWidth MSB="24" LSB="24"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y11"> <DataWidth MSB="25" LSB="25"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y12"> <DataWidth MSB="26" LSB="26"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y8"> <DataWidth MSB="27" LSB="27"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y9"> <DataWidth MSB="28" LSB="28"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y8"> <DataWidth MSB="29" LSB="29"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 --><BitLane MemType="RAMB32" Placement="X2Y9"> <DataWidth MSB="30" LSB="30"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y13"> <DataWidth MSB="31" LSB="31"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a35tcsg325-2"/>
      </Config>
      </MemInfo>
      top/cute_a7_ref_design/cute_a7_ref_design_50t.mmi 0 → 100644
      View file @ 50d6bf22
      <?xml version="1.0" encoding="UTF-8"?>
      <MemInfo Version="1" Minor="0">
      <Processor Endianness="Little" InstPath="dummy">
      <AddressSpace Name="bram" Begin="0" End="131071">
      <BusBlock>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y14"> <DataWidth MSB="0" LSB="0"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 --><BitLane MemType="RAMB32" Placement="X1Y17"> <DataWidth MSB="1" LSB="1"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y17"> <DataWidth MSB="2" LSB="2"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 --><BitLane MemType="RAMB32" Placement="X2Y15"> <DataWidth MSB="4" LSB="4"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y14"> <DataWidth MSB="5" LSB="5"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y16"> <DataWidth MSB="6" LSB="6"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y18"> <DataWidth MSB="7" LSB="7"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y15"> <DataWidth MSB="3" LSB="3"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y5"> <DataWidth MSB="8" LSB="8"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y5"> <DataWidth MSB="9" LSB="9"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y6"> <DataWidth MSB="10" LSB="10"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y6"> <DataWidth MSB="11" LSB="11"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 --><BitLane MemType="RAMB32" Placement="X2Y7"> <DataWidth MSB="12" LSB="12"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y4"> <DataWidth MSB="13" LSB="13"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 --><BitLane MemType="RAMB32" Placement="X1Y4"> <DataWidth MSB="14" LSB="14"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y3"> <DataWidth MSB="15" LSB="15"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 --><BitLane MemType="RAMB32" Placement="X1Y10"> <DataWidth MSB="16" LSB="16"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 --><BitLane MemType="RAMB32" Placement="X0Y10"> <DataWidth MSB="17" LSB="17"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 --><BitLane MemType="RAMB32" Placement="X0Y11"> <DataWidth MSB="18" LSB="18"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 --><BitLane MemType="RAMB32" Placement="X0Y12"> <DataWidth MSB="19" LSB="19"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y7"> <DataWidth MSB="20" LSB="20"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 --><BitLane MemType="RAMB32" Placement="X0Y8"> <DataWidth MSB="21" LSB="21"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 --><BitLane MemType="RAMB32" Placement="X0Y9"> <DataWidth MSB="22" LSB="22"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 --><BitLane MemType="RAMB32" Placement="X0Y7"> <DataWidth MSB="23" LSB="23"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 --><BitLane MemType="RAMB32" Placement="X2Y13"> <DataWidth MSB="24" LSB="24"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 --><BitLane MemType="RAMB32" Placement="X2Y11"> <DataWidth MSB="25" LSB="25"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 --><BitLane MemType="RAMB32" Placement="X2Y12"> <DataWidth MSB="26" LSB="26"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 --><BitLane MemType="RAMB32" Placement="X1Y8"> <DataWidth MSB="27" LSB="27"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 --><BitLane MemType="RAMB32" Placement="X1Y9"> <DataWidth MSB="28" LSB="28"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 --><BitLane MemType="RAMB32" Placement="X2Y8"> <DataWidth MSB="29" LSB="29"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 --><BitLane MemType="RAMB32" Placement="X2Y9"> <DataWidth MSB="30" LSB="30"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      <!-- */gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 --><BitLane MemType="RAMB32" Placement="X1Y13"> <DataWidth MSB="31" LSB="31"/> <AddressRange Begin="0" End="32767"/><Parity NumBits="0" ON="false"/></BitLane>
      </BusBlock>
      </AddressSpace>
      </Processor>
      <Config>
      <Option Name="Part" Val="xc7a50tcsg325-2"/>
      </Config>
      </MemInfo>
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