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White Rabbit Switch - Gateware
Commit 7303468f authored by Harvey Leicester's avatar Harvey Leicester
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afcz: endpoint directly to nic, rt_cpu i2c configures clock switch, gth and ref… 

afcz: endpoint directly to nic, rt_cpu i2c configures clock switch, gth and ref clks from HMC7044, extra debug registers
parent d88714b3
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Showing with 495 additions and 471 deletions
top/afcz_wrs_8p/afcz_wrs_8p_top.vhd
View file @ 7303468f
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top/afcz_wrs_8p/constraints.xdc
View file @ 7303468f
......@@ -249,10 +249,12 @@ set_property PACKAGE_PIN AB10 [get_ports mgtclk1_225_p_i]
#
set_property PACKAGE_PIN A11 [get_ports i2c_scl_b]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl_b]
#
set_property PULLUP TRUE [get_ports i2c_scl_b]
set_property PACKAGE_PIN A12 [get_ports i2c_sda_b]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda_b]
#
set_property PULLUP TRUE [get_ports i2c_sda_b]
#set_property PACKAGE_PIN AK33 [get_ports sfp1_prsnt_n_i]
#set_property IOSTANDARD LVCMOS12 [get_ports sfp1_prsnt_n_i]
#set_property PULLUP true [get_ports sfp1_prsnt_n_i]
......@@ -435,8 +437,8 @@ set_property IOSTANDARD LVCMOS18 [get_ports {sfp_sda_b[3]}]
#set_property DIFF_TERM_ADV TERM_100 [get_ports WR_CLK_P]
## Bank 64 voltage = 1.8V
set_property PACKAGE_PIN AT6 [get_ports clk_20m_vcxo_i]
set_property IOSTANDARD LVCMOS18 [get_ports clk_20m_vcxo_i]
#set_property PACKAGE_PIN AU26 [get_ports clk_20m_vcxo_i]
#set_property IOSTANDARD LVCMOS18 [get_ports clk_20m_vcxo_i]
set_property PACKAGE_PIN F21 [get_ports clk_aux_p_i]
set_property IOSTANDARD LVDS [get_ports clk_aux_p_i]
......@@ -454,6 +456,13 @@ set_property PACKAGE_PIN E28 [get_ports clk_helper_n_i]
set_property IOSTANDARD LVDS [get_ports clk_helper_n_i]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_helper_n_i]
set_property PACKAGE_PIN AV6 [get_ports clk_ref_n_i]
set_property IOSTANDARD LVDS [get_ports clk_ref_n_i]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_ref_n_i]
set_property PACKAGE_PIN AU6 [get_ports clk_ref_p_i]
set_property IOSTANDARD LVDS [get_ports clk_ref_p_i]
set_property DIFF_TERM_ADV TERM_100 [get_ports clk_ref_p_i]
# WR DAC 1 Bank voltage = 3.3V (on AFCZ board)
#set_property PACKAGE_PIN G10 [get_ports wr_dac1_din_o]
......@@ -487,6 +496,17 @@ set_property IOSTANDARD LVCMOS18 [get_ports wr_dac1_sclk_o]
set_property PACKAGE_PIN A30 [get_ports {wr_dac1_sync_n_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {wr_dac1_sync_n_o[0]}]
#FMC2
#set_property PACKAGE_PIN E17 [get_ports wr_dac1_din_o]
#set_property IOSTANDARD LVCMOS18 [get_ports wr_dac1_din_o]
#set_property PACKAGE_PIN E19 [get_ports wr_dac1_sclk_o]
#set_property IOSTANDARD LVCMOS18 [get_ports wr_dac1_sclk_o]
#set_property PACKAGE_PIN F18 [get_ports {wr_dac1_sync_n_o[1]}]
#set_property IOSTANDARD LVCMOS18 [get_ports {wr_dac1_sync_n_o[1]}]
#Si549 on FMC timing board (using si57x nets...)
set_property PACKAGE_PIN H26 [get_ports si57x_scl_b]
......@@ -526,8 +546,6 @@ set_property IOSTANDARD LVDS [get_ports hmc_sync_p_o]
set_property PACKAGE_PIN B28 [get_ports hmc_sync_n_o]
set_property IOSTANDARD LVDS [get_ports hmc_sync_n_o]
# WR DAC 2 Bank voltage = 3.3V
......
top/bare_top/scb_top_bare.vhd
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top/bare_top/wrs_sdb_pkg.vhd
View file @ 7303468f
......@@ -328,7 +328,7 @@ package wrs_sdb_pkg is
f_xwb_bridge_layout_sdb(true, c_epbar_layout, c_epbar_sdb_address);
-- WRS main crossbar
constant c_layout : t_sdb_record_array(15+4 downto 0) :=
constant c_layout : t_sdb_record_array(16+4 downto 0) :=
(0 => f_sdb_embed_bridge(c_rtbar_bridge_sdb, x"00000000"), --RT subsystem
1 => f_sdb_embed_device(c_xwr_nic_sdb, x"00020000"), --NIC
2 => f_sdb_embed_bridge(c_epbar_bridge_sdb, x"00030000"), --Endpoints
......@@ -345,10 +345,11 @@ package wrs_sdb_pkg is
13 => f_sdb_embed_device(c_xwrsw_watchdog_sdb, x"0005a000"), --Watchdog
14 => f_sdb_embed_device(c_xswc_swcore_sdb, x"0005b000"), --SWcore
15 => f_sdb_embed_device(c_xwr_sfp_ctrl_sdb, x"0005c000"), --SFP Ctrl
16 => f_sdb_embed_repo_url(c_sdb_repo_url),
17 => f_sdb_embed_synthesis(c_sdb_top_syn_info),
18 => f_sdb_embed_synthesis(c_sdb_general_cores_syn_info),
19 => f_sdb_embed_synthesis(c_sdb_wr_cores_syn_info));
16 => f_sdb_embed_device(c_xwb_gpio_port_sdb, x"0005d000"), --Debug GPIO
17 => f_sdb_embed_repo_url(c_sdb_repo_url),
18 => f_sdb_embed_synthesis(c_sdb_top_syn_info),
19 => f_sdb_embed_synthesis(c_sdb_general_cores_syn_info),
20 => f_sdb_embed_synthesis(c_sdb_wr_cores_syn_info));
constant c_sdb_address : t_wishbone_address := x"00070000";
end wrs_sdb_pkg;
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