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W
White Rabbit Switch - Gateware
Commit 87f02277 authored by li hongming's avatar li hongming
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add support for WRS-LJ. 

    There are three types of wrs: normal wrs(mark as wrs), wrs with LJD
(mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ).
    lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ.
    lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD.
        lj_osc_freq_i=111 means WRSLJ.
        lj_osc_freq_i=others means WRS-LJD.

    lj_osc_freq_i[2 downto 0] need to be pulled up.
parent d315bf7b
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Showing with 113 additions and 21 deletions
modules/wrsw_hwiu/gw_ver_pkg.vhd
View file @ 87f02277
...@@ -2,8 +2,8 @@ library ieee; ...@@ -2,8 +2,8 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
--generated automatically by gen_ver.py script-- --generated automatically by gen_ver.py script--
package hwver_pkg is package hwver_pkg is
constant c_build_date : std_logic_vector(31 downto 0) := x"06041400"; constant c_build_date : std_logic_vector(31 downto 0) := x"0e051400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"04e89257"; constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"092bce2d";
constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3"; constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65"; constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
end package; end package;
top/bare_top/scb_top_bare.vhd
View file @ 87f02277
...@@ -1335,7 +1335,7 @@ begin ...@@ -1335,7 +1335,7 @@ begin
ljd_detected_o <= ljd_detected; ljd_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected -- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data) dac_redirection : process (ljd_detected, ljd_osc_freq_i, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin begin
if (ljd_detected = '0') then if (ljd_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n; dac_main_sync_n_o <= dac_main_sync_n;
...@@ -1344,6 +1344,14 @@ begin ...@@ -1344,6 +1344,14 @@ begin
ljd_dac_main_sync_n_o <= '0'; ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0'; ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0'; ljd_dac_main_data_o <= '0';
else
if(ljd_osc_freq_i="111") then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else else
dac_main_sync_n_o <= '0'; dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0'; dac_main_sclk_o <= '0';
...@@ -1352,6 +1360,7 @@ begin ...@@ -1352,6 +1360,7 @@ begin
ljd_dac_main_sclk_o <= dac_main_sclk; ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data; ljd_dac_main_data_o <= dac_main_data;
end if; end if;
end if;
end process; end process;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 87f02277
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