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W
White Rabbit Switch - Gateware
Commit 87f02277 authored by li hongming's avatar li hongming
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add support for WRS-LJ. 

    There are three types of wrs: normal wrs(mark as wrs), wrs with LJD
(mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ).
    lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ.
    lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD.
        lj_osc_freq_i=111 means WRSLJ.
        lj_osc_freq_i=others means WRS-LJD.

    lj_osc_freq_i[2 downto 0] need to be pulled up.
parent d315bf7b
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Showing with 113 additions and 21 deletions
modules/wrsw_hwiu/gw_ver_pkg.vhd
View file @ 87f02277
......@@ -2,8 +2,8 @@ library ieee;
use ieee.std_logic_1164.all;
--generated automatically by gen_ver.py script--
package hwver_pkg is
constant c_build_date : std_logic_vector(31 downto 0) := x"06041400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"04e89257";
constant c_build_date : std_logic_vector(31 downto 0) := x"0e051400";
constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"092bce2d";
constant c_gencores_ver : std_logic_vector(31 downto 0) := x"0dcc7cc3";
constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"08299d65";
end package;
top/bare_top/scb_top_bare.vhd
View file @ 87f02277
......@@ -83,8 +83,8 @@ entity scb_top_bare is
-- for re-phasing the 10 MHz input as well as clocking the
clk_aux_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -1335,7 +1335,7 @@ begin
ljd_detected_o <= ljd_detected;
-- Redirect DAC output if external board detetected
dac_redirection : process (ljd_detected, dac_main_sync_n, dac_main_sclk, dac_main_data)
dac_redirection : process (ljd_detected, ljd_osc_freq_i, dac_main_sync_n, dac_main_sclk, dac_main_data)
begin
if (ljd_detected = '0') then
dac_main_sync_n_o <= dac_main_sync_n;
......@@ -1345,12 +1345,21 @@ begin
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ljd_dac_main_sync_n_o <= dac_main_sync_n;
ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data;
if(ljd_osc_freq_i="111") then
dac_main_sync_n_o <= dac_main_sync_n;
dac_main_sclk_o <= dac_main_sclk;
dac_main_data_o <= dac_main_data;
ljd_dac_main_sync_n_o <= '0';
ljd_dac_main_sclk_o <= '0';
ljd_dac_main_data_o <= '0';
else
dac_main_sync_n_o <= '0';
dac_main_sclk_o <= '0';
dac_main_data_o <= '0';
ljd_dac_main_sync_n_o <= dac_main_sync_n;
ljd_dac_main_sclk_o <= dac_main_sclk;
ljd_dac_main_data_o <= dac_main_data;
end if;
end if;
end process;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 87f02277
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