CI: update Manifest.py and YML file

Manifest: - Before syn: add execution of script to generate files with repo versions - After syn: add generation of bin file YML: - synthesize 8 ports always - synthesize 18 ports when called manually - simulate when called manually

CI: update Manifest.py and YML file
Manifest: - Before syn: add execution of script to generate files with repo versions - After syn: add generation of bin file YML: - synthesize 8 ports always - synthesize 18 ports when called manually - simulate when called manually
bd0d0d31 · Maciej Lipinski · a9b9ce21 · bd0d0d31 · bd0d0d31 · bd0d0d31
Commit bd0d0d31 authored Nov 30, 2023 by Maciej Lipinski
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.gitlab-ci.yml .gitlab-ci.yml +70 -65

Manifest.py syn/scb_18ports/Manifest.py +2 -0

Manifest.py syn/scb_8ports/Manifest.py +3 -0

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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -2,73 +2,78 @@ variables:
        GIT_SUBMODULE_STRATEGY: normal

 stages:
-# - sim
+ - sim
 - syn

-#job_scb_top_sim:
-#    stage: sim
-#    tags:
-#     - modelsim_10.2a
-#    script:
-#     - /entrypoint.sh
-#     - source ~/setup_modelsim.sh
-#     - git submodule sync & git submodule update --init
-#     - apt-get install -y python
-#     - cd top/bare_top
-#     - python gen_sdbsyn.py --project wr_switch
-#     - cd ../../
-#     - cd sim
-#     - ln -s ../ip_cores/wr-cores/sim wr-hdl
-#     - cd ../testbench/scb_top
-#     - cp /opt/compiled_libs_ise14.7/modelsim.ini .
-#     - hdlmake makefile
-#     - make
-#     - vsim -c -do run.do
+job_scb_top_sim:
+   stage: sim
+   when: manual
+   tags:
+    - modelsim_10.2a
+   script:
+    - /entrypoint.sh
+    - source ~/setup_modelsim.sh
+    - git submodule sync & git submodule update --init
+    - apt-get install -y python
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat ../../modules/wrsw_hwiu/gw_ver_pkg.vhd
+    - cd ../../
+    - cd sim
+    - ln -s ../ip_cores/wr-cores/sim wr-hdl
+    - cd ../testbench/scb_top
+    - cp /opt/compiled_libs_ise14.7/modelsim.ini .
+    - hdlmake makefile
+    - make
+    - vsim -c -do run.do

 job_scb_top_8p_syn:
-    stage: syn
-    tags:
-     - xilinx_ISE_14.7 
-    script:
-     - /entrypoint.sh
-     - source ~/setup_ise147.sh
-     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-     - cd top/bare_top
-     - python gen_sdbsyn.py --project wr_switch
-     - cat synthesis_descriptor.vhd
-     - cd ../../syn/scb_8ports 
-     - hdlmake makefile 
-     - make
-    artifacts:
-     name: SCB_TOP_8P_CI_$CI_JOB_ID
-     paths:
-     - syn/scb_8ports/*.syr
-     - syn/scb_8ports/*.mrp
-     - syn/scb_8ports/*.bit
-     - syn/scb_8ports/*.bin
-     - syn/scb_8ports/*.par
-     - syn/scb_8ports/*.twr
+   stage: syn
+   tags:
+    - xilinx_ISE_14.7 
+   script:
+    - /entrypoint.sh
+    - source ~/setup_ise147.sh
+    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat synthesis_descriptor.vhd
+    - cat ../../modules/wrsw_hwiu/gw_ver_pkg.vhd
+    - cd ../../syn/scb_8ports 
+    - hdlmake makefile 
+    - make
+   artifacts:
+    name: SCB_TOP_8P_CI_$CI_JOB_ID
+    paths:
+    - syn/scb_8ports/*.syr
+    - syn/scb_8ports/*.mrp
+    - syn/scb_8ports/*.bit
+    - syn/scb_8ports/*.bin
+    - syn/scb_8ports/*.par
+    - syn/scb_8ports/*.twr

-#job_scb_top_18p_syn:
-#    stage: syn
-#    tags:
-#     - xilinx_ISE_14.7 
-#    script:
-#     - /entrypoint.sh
-#     - source ~/setup_ise147.sh
-#     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-#     - cd top/bare_top
-#     - python gen_sdbsyn.py --project wr_switch
-#     - cat synthesis_descriptor.vhd
-#     - cd ../../syn/scb_18ports 
-#     - hdlmake makefile 
-#     - make
-#    artifacts:
-#     name: SCB_TOP_8P_CI_$CI_JOB_ID
-#     paths:
-#     - syn/scb_18ports/*.syr
-#     - syn/scb_18ports/*.mrp
-#     - syn/scb_18ports/*.bit
-#     - syn/scb_18ports/*.bin
-#     - syn/scb_18ports/*.par
-#     - syn/scb_18ports/*.twr
+job_scb_top_18p_syn:
+   stage: syn
+   when: manual
+   tags:
+    - xilinx_ISE_14.7 
+   script:
+    - /entrypoint.sh
+    - source ~/setup_ise147.sh
+    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat synthesis_descriptor.vhd
+    - cat ../../modules/wrsw_hwiu/gw_ver_pkg.vhd
+    - cd ../../syn/scb_18ports 
+    - hdlmake makefile 
+    - make
+   artifacts:
+    name: SCB_TOP_8P_CI_$CI_JOB_ID
+    paths:
+    - syn/scb_18ports/*.syr
+    - syn/scb_18ports/*.mrp
+    - syn/scb_18ports/*.bit
+    - syn/scb_18ports/*.bin
+    - syn/scb_18ports/*.par
+    - syn/scb_18ports/*.twr
--- a/syn/scb_18ports/Manifest.py
+++ b/syn/scb_18ports/Manifest.py
@@ -10,6 +10,8 @@ syn_grade = "-1"
 syn_package = "ff1156"
 syn_top = "scb_top_synthesis"
 syn_project = "test_scb.xise"
+syn_pre_project_cmd="python ../../modules/wrsw_hwiu/gen_ver.py"
+syn_post_bitstream_cmd="bitgen -intstyle ise -f scb_top_synthesis.ut -g Binary:yes scb_top_synthesis.ncd"

 modules = { "local" : [ "../../top/scb_18ports",
                        "../../ip_cores/general-cores",

--- a/syn/scb_8ports/Manifest.py
+++ b/syn/scb_8ports/Manifest.py
@@ -10,7 +10,10 @@ syn_grade = "-1"
 syn_package = "ff1156"
 syn_top = "scb_top_synthesis"
 syn_project = "test_scb.xise"
+syn_pre_project_cmd="python ../../modules/wrsw_hwiu/gen_ver.py"
+syn_post_bitstream_cmd="bitgen -intstyle ise -f scb_top_synthesis.ut -g Binary:yes scb_top_synthesis.ncd"

 modules = { "local" : [ "../../top/scb_8ports",
                        "../../ip_cores/general-cores",
                        "../../ip_cores/wr-cores"] }
+