This page gives an overview of how to build gateware for the WRSv4. Further information on simulation and the directory structure can be found on the WRSv3 Wiki.
Prerequisites
To build the gateware the following tools are required:
- git
- Xilinx Vivado version 2022.2 or above
Synthesis WRSv4
Download the HDL sources
git clone https://ohwr.org/project/wr-switch-hdl.git
cd wr-switch-hdl
git checkout wrs-v4-dev
git submodule update --init --remote
Generate SDB Metadata package with project information
cd top/bare_top
./gen_sdbsyn.py --user <your name> --project WRSv4 --ver <Vivado version>
Generate info about repo commits
cd ../../modules/wrsw_hwiu
./gen_ver.py
Run the synthesis
cd ../../syn/wrsv4_bringup
./build_bitstream.sh
This script sets up the environment, assuming Vivado install is in /tools/Xilinx/Vivado/2022.2
, and calls the main build.tcl
script. You can change the paths to suite your installation.
Alternatively, you can call the build script directly from the tcl console of Vivado with the command:
source build.tcl
Outputs are written to the /syn/wrsv4_bringup/build
directory.
The output bitstream will be written to /build/wrsv4_bringup.bit
Design checkpoints are written to /build/dcp/
Reports are written to /build/reports/
XSA archive required for software boot image is written to /build/wrsv4_bringup.xsa
Note: the files committed here are in development and have not yet been tested on the WRSv4 hardware.