Updated sigdel value

With this value, the WRS-LJ will show a stable 10 MHz with an adequate duty cycle. An incorrect value will make the 10 MHz output jittery and the duty cycle erratic.

Updated sigdel value
With this value, the WRS-LJ will show a stable 10 MHz with an adequate duty cycle. An incorrect value will make the 10 MHz output jittery and the duty cycle erratic.
98457732 · José López Jiménez · 9fc9687e · 98457732 · 98457732
Commit 98457732 authored Apr 25, 2022 by José López Jiménez
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Kconfig Kconfig +1 -1

wrs_release_defconfig configs/wrs_release_defconfig +1 -1

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--- a/Kconfig
+++ b/Kconfig
@@ -997,7 +997,7 @@ config WRSAUXCLK_CSHIFT

 config WRSAUXCLK_SIGDEL
 	string "Signal delay of the generated clock signal"
-	default "0"
+	default "5"
 	help
 	  --sigdel parameter of wrs_auxclk
 	  Clock signal generated from the FPGA is cleaned by a discrete

--- a/configs/wrs_release_defconfig
+++ b/configs/wrs_release_defconfig
@@ -681,7 +681,7 @@ CONFIG_SNMP_TEMP_THOLD_PSR=80
 CONFIG_WRSAUXCLK_FREQ="10"
 CONFIG_WRSAUXCLK_DUTY="0.5"
 CONFIG_WRSAUXCLK_CSHIFT="30"
-CONFIG_WRSAUXCLK_SIGDEL="0"
+CONFIG_WRSAUXCLK_SIGDEL="5"
 CONFIG_WRSAUXCLK_PPSHIFT="0"

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