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Software for White Rabbit PTP Core
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09798d30
Commit
09798d30
authored
Jun 25, 2021
by
Peter Jansweijer
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add safe tx phase offset for SPEC7
parent
a96ebd1c
Pipeline
#4815
failed with stage
in 25 seconds
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1
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3
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phy_calibration.c
boards/spec7/phy_calibration.c
+8
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boards/spec7/phy_calibration.c
View file @
09798d30
...
...
@@ -55,6 +55,12 @@
#define FSM_EARLY_LINK_UP_TIMEOUT_MS 100
#define FSM_STABILIZE_TIMEOUT_MS 100
// TX Target phase for SPEC7 is measured TXOUTCLK_OUT of the PHY.
// For SPEC7 clk_ref_62m5 and TXOUTCLK_OUT are phase locked but have an offset.
// Add a safe offset such that the TxData and TxK (clk_ref_62m5 domain) are
// safely clocked into the PHY (TXOUTCLK_OUT domain).
#define TX_PHASE_OFFSET 2000
struct
wrc_port_tx_setup_state
{
int
state
;
...
...
@@ -226,7 +232,7 @@ static int tx_fsm_update()
{
//pr_info("Using phase from file :%d\n",
//fsm->cal_saved_phase);
fsm
->
expected_phase
=
fsm
->
cal_saved_phase
;
fsm
->
expected_phase
=
fsm
->
cal_saved_phase
+
TX_PHASE_OFFSET
;
fsm
->
tollerance
=
150
;
/*ps, bins are 200 ps wide*/
}
else
// find a sane default
...
...
@@ -485,4 +491,4 @@ void phy_calibration_disable()
{
tx_state
.
state
=
TX_SETUP_STATE_DISABLED
;
rx_state
.
state
=
RX_SETUP_STATE_DISABLED
;
}
\ No newline at end of file
}
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