update phy_calibration since family7-gtx-lp phy now uses WB bus for LPDC regs

c1de7e63 · Peter Jansweijer · 5b85627f · c1de7e63 · c1de7e63 · c1de7e63
Commit c1de7e63 authored Aug 29, 2023 by Peter Jansweijer
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board.c boards/spec7/board.c +52 -26

board.h boards/spec7/board.h +21 -52

phy_calibration.c boards/spec7/phy_calibration.c +297 -246

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--- a/boards/spec7/board.c
+++ b/boards/spec7/board.c
+/*
+ * This work is part of the White Rabbit project
+ *
+ * Copyright (C) 2022 Nikhef (www.Nikhef.nl)
+ * Author: Peter Jansweijer <peterj@nikhef.nl> based on work
+ * from Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
+ *
+ * This program is free software: you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation, either version 3 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
 #include "board.h"
+#include "wrc.h"
+#include "wrc-debug.h"
+#include "wrpc.h"
 #include "dev/bb_spi.h"
 #include "dev/spi_flash.h"
 #include "dev/bb_i2c.h"
 #include "dev/i2c_eeprom.h"
 #include "dev/syscon.h"
+#include "dev/endpoint.h"
 #include "storage.h"
-#include <wrc_ptp.h>
-#include "spll_defs.h"
-#include "spll_common.h"
-#include "hw/pps_gen_regs.h"
+#include "softpll_ng.h"

-struct spec7_board board;
+struct
+{
+    struct gpio_device gpio_aux;
+    struct spi_bus spi_ltc6950;
+    struct ltc695x_device ltc6950_pll;
+    int pll_wr_mode;
+} board;

 static struct gpio_pin pin_pll_cs_n_o        = { &board.gpio_aux, 0 };
 static struct gpio_pin pin_pll_mosi_o        = { &board.gpio_aux, 1 };
 static struct gpio_pin pin_pll_miso_i        = { &board.gpio_aux, 2 };
 static struct gpio_pin pin_pll_sck_o         = { &board.gpio_aux, 3 };
 static struct gpio_pin pin_pll_reset_n_o     = { &board.gpio_aux, 4 };
-static struct gpio_pin pin_pll_lock_i        = { &board.gpio_aux, 5 };
-static struct gpio_pin pin_pll_status_i      = { &board.gpio_aux, 6 };
+//static struct gpio_pin pin_pll_lock_i        = { &board.gpio_aux, 5 };
+//static struct gpio_pin pin_pll_status_i      = { &board.gpio_aux, 6 };
 static struct gpio_pin pin_pll_sync_o        = { &board.gpio_aux, 7 };
 static struct gpio_pin pin_pll_wr_mode0_o    = { &board.gpio_aux, 8 };
 static struct gpio_pin pin_pll_wr_mode1_o    = { &board.gpio_aux, 9 };
@@ -29,9 +57,9 @@ static struct gpio_pin pin_pll_even_odd_n_i  = { &board.gpio_aux, 13 };
 static struct gpio_pin pin_pll_sync_done_i   = { &board.gpio_aux, 14 };

 #include "configs/ltc6950_defs.h" 
-static struct ltc6950_config ltc6950_base_config =
+static struct ltc695x_config ltc6950_base_config =
 #include "configs/ltc6950_base_config.h" 
-static struct ltc6950_config ltc6950_ext_10mhz_config =
+static struct ltc695x_config ltc6950_ext_10mhz_config =
 #include "configs/ltc6950_ext_10mhz_config.h" 

 #define PLL_EVEN_ODD_TIMEOUT_MS 10000
@@ -45,7 +73,7 @@ timeout_t pll_sync_timeout;

 //volatile struct softpll_state softpll;

-void spec7_set_pll_wr_mode(int wrc_ptp_mode)
+void board_pre_pll_lock(int wrc_ptp_mode)
 {
    int pll_wr_mode;
    int mode_hpsec_gm = 0;
@@ -82,18 +110,18 @@ void spec7_set_pll_wr_mode(int wrc_ptp_mode)

    // ltc6950 initialization depending on wrc_ptp_mode
    board_dbg("Initialize ltc6950.\n");
-    if (wrc_ptp_mode == WRC_MODE_MASTER | mode_hpsec_gm == 1) {
+    if ((wrc_ptp_mode == WRC_MODE_MASTER) | (mode_hpsec_gm == 1)) {
        // 10 MHZ from TCXO (WRC_MODE_MASTER) on outputs 0, 1, 2
        // or (for HPSEC in WRC_MODE GM) External 10 MHZ In (Bulls-Eye B03/B04) => 125 MHz
-        ltc6950_configure(&board.ltc6950_pll, &ltc6950_ext_10mhz_config);
-        while ((ltc6950_read(&board.ltc6950_pll,  0x00) & LTC6950_LOCK) == 0);
+        ltc695x_configure(&board.ltc6950_pll, &ltc6950_ext_10mhz_config);
+        while ((ltc695x_read(&board.ltc6950_pll,  0x00) & LTC6950_LOCK) == 0);
        board_dbg("ltc6950 locked.\n");
 #if defined(CONFIG_HPSEC_GM)
        pll_sync();
 #endif
    } else {
        // Forward 125 MHz VCXO_REFCLK at CLK input to outputs 0, 1, 2
-        ltc6950_configure(&board.ltc6950_pll, &ltc6950_base_config);
+        ltc695x_configure(&board.ltc6950_pll, &ltc6950_base_config);
    }

    board_dbg("Select ltc6950 output as clk_sys source.\n");
@@ -102,7 +130,7 @@ void spec7_set_pll_wr_mode(int wrc_ptp_mode)
    timer_delay_ms(10);
 }

-int pll_sync()
+int pll_sync(void)
 {
    // Used in HPSEC Grand Master mode where external 10MHz generates 125MHz.
    // 125MHz is not an integer multiple of 10MHz so it has two lock modes: even/odd.
@@ -112,10 +140,10 @@ int pll_sync()
    while (gen_gpio_in( &pin_pll_even_odd_n_i ) == 0) {
        // Reset the PLL (RES6950 clears itself)
        board_dbg("Reset ltc6950...\n");
-        ltc6950_write( &board.ltc6950_pll, 0x03, 4);
+        ltc695x_write( &board.ltc6950_pll, 0x03, 4);
        timer_delay_ms(1);
-        ltc6950_configure(&board.ltc6950_pll, &ltc6950_ext_10mhz_config);
-        while ((ltc6950_read(&board.ltc6950_pll,  0x00) & LTC6950_LOCK) == 0);
+        ltc695x_configure(&board.ltc6950_pll, &ltc6950_ext_10mhz_config);
+        while ((ltc695x_read(&board.ltc6950_pll,  0x00) & LTC6950_LOCK) == 0);
        timer_delay_ms(1000);  // wait for next PPS
        if ( tmo_expired(&pll_even_odd_timeout)) {
            pp_printf("TIMEOUT: External 10MHz/1PPS lock to \"even\" 125MHz clock cycle.\n");
@@ -158,6 +186,7 @@ int pll_sync()
    return 1;
 }

+/*
 int post_pll_lock(int wrc_ptp_mode)
 {
 #if defined(CONFIG_HPSEC_GM)
@@ -179,7 +208,7 @@ int post_pll_lock(int wrc_ptp_mode)

    return 1;
 }
-
+*/

 int spec7_init()
 {
@@ -205,18 +234,18 @@ int spec7_init()
        &pin_pll_sck_o,
        100 );

-    ltc6950_init(&board.ltc6950_pll, &board.spi_ltc6950);
+    ltc695x_init(&board.ltc6950_pll, &board.spi_ltc6950);

    // Reset the PLL (RES6950 clears itself)
-    ltc6950_write( &board.ltc6950_pll, 0x03, 4);
+    ltc695x_write( &board.ltc6950_pll, 0x03, 4);
    timer_delay_ms(1);

-    int id = ltc6950_read( &board.ltc6950_pll, 0x16 );
+    int id = ltc695x_read( &board.ltc6950_pll, 0x16 );
    if( id != 0x65 )
    {
        board_dbg("detect LTC6950: ID %x should be %x\n", id, 0x65 );
    } else {
-        spec7_set_pll_wr_mode(WRC_MODE_SLAVE);
+        board_pre_pll_lock(WRC_MODE_SLAVE);
    }

    return 0;
@@ -268,9 +297,6 @@ int wrc_board_init()
    return 0;
 }

-extern int phy_calibration_poll();
-extern void phy_calibration_init();
-
 int wrc_board_create_tasks()
 {
    wrc_task_create( "phy-cal", phy_calibration_init, phy_calibration_poll );

--- a/boards/spec7/board.h
+++ b/boards/spec7/board.h
@@ -7,31 +7,20 @@
 #define __BOARD_SPEC7_H

 #include "dev/gpio.h"
-#include "dev/ltc6950.h"
+#include "dev/ltc695x.h"

 /*
 * This is meant to be automatically included by the Makefile,
 * when wrpc-sw is build for wrc (node) -- as opposed to wrs (switch)
 */

-/* Fixed base addresses */
-#define BASE_MINIC            0x40000
-#define BASE_EP               0x40100
-#define BASE_SOFTPLL          0x40200
-#define BASE_PPS_GEN          0x40300
-#define BASE_SYSCON           0x40400
-#define BASE_UART             0x40500
-#define BASE_ONEWIRE          0x40600
-//#define BASE_ETHERNOBE_CFG    0x40700
-#define BASE_AUXWB            0x48000
-
 /* SPEC7 WB bus behind wr-cores Aux WB bus */
 #define BASE_GPIO            (BASE_AUXWB + 0x000)

 /* Board-specific parameters */
 #define TICS_PER_SECOND 1000

-/* WR Core system/CPU clock frequency in Hz */
+/* WR Core system/CPU clock frequency in Hz (clk_sys) */
 #define CPU_CLOCK 62500000ULL

 /* WR Reference clock period (picoseconds) and frequency (Hz) */
@@ -40,70 +29,50 @@
 #define REF_CLOCK_PERIOD_PS 16000
 #define REF_CLOCK_FREQ_HZ 62500000

-/* Baud rate of the builtin UART (does not apply to the VUART) */
-#define UART_BAUDRATE 115200ULL
-
 /* Maximum number of simultaneously created sockets */
 #define NET_MAX_SOCKETS 12

 /* Socket buffer size, determines the max. RX packet size */
 #define NET_MAX_SKBUF_SIZE 512

-/* Number of auxillary clock channels - usually equal to the number of FMCs */
-#define NUM_AUX_CLOCKS 1
-
 /* spll parameter that are board-specific */
 // SPEC7 has GENERIC_PHY_16BIT
-#  define BOARD_DIVIDE_DMTD_CLOCKS    0
+#define BOARD_DIVIDE_DMTD_CLOCKS      0

+/* Number of reference channels (RX clocks) */
 #define BOARD_MAX_CHAN_REF            1
+/* Number of external pll that can be disciplined */
 #define BOARD_MAX_CHAN_AUX            2
+/* Should be the same as reference channels */
 #define BOARD_MAX_PTRACKERS           1

-#ifdef CONFIG_IP
-#define HAS_IP 1
-#else
-#define HAS_IP 0
-#endif
-
-#ifdef CONFIG_ABSCAL
-#define HAS_ABSCAL 1
-#else
-#define HAS_ABSCAL 0
-#endif
-
-#define CONFIG_DISALLOW_LONG_DIVISION
-
-#define BOARD_MAX_CONSOLE_DEVICES 1
+/* Events are not used on this platform */
+#define BOARD_USE_EVENTS 0

+/* Use one uart at 115200 baud. May add extra uart. */
+#define BOARD_CONSOLE_DEVICES 1
 #define CONSOLE_UART_BAUDRATE 115200

-#define SDB_ADDRESS 0x30000
+/* Maximum number of files in the sdb filesystem.
+   Need at least 4: ., sfp database, init script and calibration
+   MAC address could also be written on sdbfs. */
+#define SDBFS_REC 5

+/* Specific to this board (see board.c) */
+/* I2C address of the storage eeprom */
 #define FMC_EEPROM_ADR 0x50

-#define SDBFS_REC 5
-
 // PLL WR_MODE options:
 #  define PLL_WR_MODE_MASTER 1
 #  define PLL_WR_MODE_SLAVE 2
 #  define PLL_WR_MODE_GM 3
 
-void spec7_set_pll_wr_mode(int pll_wr_mode);
+void board_pre_pll_lock(int pll_wr_mode);
 int  spec7_init(void);

-struct spec7_board
-{
-    struct gpio_device gpio_aux;
-
-    struct spi_bus spi_ltc6950;
-
-    struct ltc6950_device ltc6950_pll;
-
-    int pll_wr_mode;
-};
-
-void sdb_find_devices(void);
-void sdb_print_devices(void);
+extern int phy_calibration_poll(void);
+extern void phy_calibration_init(void);
+extern void phy_calibration_disable(void);
+extern int phy_calibration_done(void);

 #endif /* __BOARD_SPEC7_H */
--- a/boards/spec7/phy_calibration.c
+++ b/boards/spec7/phy_calibration.c