Added latches for PM control (fixes #1438)
Used LPC1768 ADCs for extra voltage monitoring (fixes #1432 and #1111)

This required some pin changes in the LPC1768. Also, did some improvements in CPU.SchDoc layout.

Fixes #1440

Fixes #1439

Fixes #1433

As discussed in #1434 (note-3) issues.

This should avoid problem in circuits with 10k pull ups.

Fixes #1428

Added newn JTAG switch and USB Uart programmer. Reassigned MMC pins accordingly.

leave only License file, in txt format instead of pdf

avoid version name on filename

keep coherence with other open-hardware projects

leave only files related to the AFC project itself

structure following the pattern DIG

Added OHL license on the schematics
updated mounted/not mounted designators.

fixed some bugs

All RC come from CERN library
Seriously limited BOM
Almost all issues solved
PCB - acute angles removed
improved plane layout- limited cutouts over high speed signals
added OutJob file

P3V3 aux regulator added in stand-alone mode
Port0/1 and 2-lane FP2 operation now possible
quad 116 connected to the clock crossbar
lot of small bugs fixed according to "issues" list

inverted all HPC lines

detected swapped RTM connectors - some work need to be done on layout
version without polygons to reduce PCB size and to make checking easier

wrong voltage measurement on FMC P12V - before the switch
Added JTAG support for RTM_CON
Added RTM power switches and I2C buffer
moved both USB ports to the front panel
swapped GTP - FP1 and FP2 to optimize FPGA timings
cleaned net names in GTP schematic