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Lucas Russo authored
Two registers were added/modified. The most important one is the ddr3_end_addr register, which is written by the bus to indicate the maximum address in which the module is allowed to write. The second one is the modification from 16-bit to 32-bit in trig_data_thres register. With this, we can compare the data threshold to any of the input channels, up to 32-bit.
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