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Commit ad0c3a74 authored by Lucas Russo's avatar Lucas Russo
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wb_acq_core/wbgen: add registers for triggered acquisition 

Two registers were added/modified. The most important one is
the ddr3_end_addr register, which is written by the bus to indicate
the maximum address in which the module is allowed to write.
The second one is the modification from 16-bit to 32-bit in
trig_data_thres register. With this, we can compare the data
threshold to any of the input channels, up to 32-bit.
parent 1b220cd5
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hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core.wb
View file @ ad0c3a74
......@@ -85,7 +85,6 @@ peripheral {
prefix = "fsm_state";
type = SLV;
size = 3;
align = 8;
clock = "fs_clk_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -168,7 +167,6 @@ peripheral {
};
};
reg {
name = "Trigger configuration";
prefix = "trig_cfg";
......@@ -229,17 +227,21 @@ peripheral {
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 10;
size = 26;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Trigger data threshold";
prefix = "trig_data_thres";
field {
name = "Threshold for internal trigger";
description = "Treated as binary two's complement and compared to raw ADC data";
prefix = "int_trig_thres";
description = "Treated as binary two's complement and compared to the \nspecified channel data";
type = SLV;
size = 16;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fs_clk_i";
......@@ -370,15 +372,34 @@ peripheral {
type = SLV;
size = 32;
-- This clock is 2x the sys_clock and a simple 2-stage synchronizer won't help here.
-- So, we just ignore that this register is in a differente domain and hope for the best.
-- Just kidding. Actually, this is as not as bad as it seems, as this is just a
-- configuration register that is ONLY read upon a fully synchronous strobe "acq_start"
-- So, we just ignore that this register is in a different domain and hope for the best,
-- as this is just a configuration register that is ONLY read upon a fully synchronous
-- strobe "acq_start".
clock = "ext_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "DDR3 End Address";
prefix = "ddr3_end_addr";
field {
name = "DDR3 End Address";
description = "End address in DDR3 memory for the next acquisition.\nMust be word aligned (2 LSB zeroed)";
type = SLV;
size = 32;
-- This clock is 2x the sys_clock and a simple 2-stage synchronizer won't help here.
-- So, we just ignore that this register is in a different domain and hope for the best,
-- as this is just a configuration register that is ONLY read upon a fully synchronous
-- strobe "acq_start".
clock = "ext_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Acquisition channel control";
prefix = "acq_chan_ctl";
......
hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs_pkg.vhd
View file @ ad0c3a74
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : acq_core_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from acq_core.wb
-- Created : Sat Dec 7 04:09:07 2013
-- Created : Tue Aug 18 18:11:49 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
......@@ -58,8 +58,8 @@ package acq_core_wbgen2_pkg is
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_sw_trig_en_o : std_logic;
trig_cfg_int_trig_sel_o : std_logic_vector(1 downto 0);
trig_cfg_reserved_o : std_logic_vector(9 downto 0);
trig_cfg_int_trig_thres_o : std_logic_vector(15 downto 0);
trig_cfg_reserved_o : std_logic_vector(25 downto 0);
trig_data_thres_o : std_logic_vector(31 downto 0);
trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
......@@ -68,6 +68,7 @@ package acq_core_wbgen2_pkg is
pre_samples_o : std_logic_vector(31 downto 0);
post_samples_o : std_logic_vector(31 downto 0);
ddr3_start_addr_o : std_logic_vector(31 downto 0);
ddr3_end_addr_o : std_logic_vector(31 downto 0);
acq_chan_ctl_which_o : std_logic_vector(4 downto 0);
end record;
......@@ -83,7 +84,7 @@ package acq_core_wbgen2_pkg is
trig_cfg_sw_trig_en_o => '0',
trig_cfg_int_trig_sel_o => (others => '0'),
trig_cfg_reserved_o => (others => '0'),
trig_cfg_int_trig_thres_o => (others => '0'),
trig_data_thres_o => (others => '0'),
trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
......@@ -92,6 +93,7 @@ package acq_core_wbgen2_pkg is
pre_samples_o => (others => '0'),
post_samples_o => (others => '0'),
ddr3_start_addr_o => (others => '0'),
ddr3_end_addr_o => (others => '0'),
acq_chan_ctl_which_o => (others => '0')
);
function "or" (left, right: t_acq_core_in_registers) return t_acq_core_in_registers;
......@@ -102,11 +104,11 @@ end package;
package body acq_core_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
if x = '1' then
return '1';
else
return x;
end if;
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
......
hdl/modules/dbe_wishbone/wb_acq_core/wbgen/build_wb.sh
View file @ ad0c3a74
#!/bin/bash
wbgen2 -V acq_core_regs.vhd -H record -p acq_core_regs_pkg.vhd -K ../../../../sim/regs/wb_acq_core_regs.vh -s struct -C wb_acq_core_regs.h -f html -D doc/wb_acq_core.html acq_core.wb
wbgen2 -V acq_core_regs.vhd -H record -p acq_core_regs_pkg.vhd -K ../../../../sim/regs/wb_acq_core_regs.vh -s defines -C wb_acq_core_regs.h -f html -D doc/wb_acq_core.html acq_core.wb
hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs.h
View file @ ad0c3a74
......@@ -3,7 +3,7 @@
* File : wb_acq_core_regs.h
* Author : auto-generated by wbgen2 from acq_core.wb
* Created : Sat Dec 7 04:09:07 2013
* Created : Tue Aug 18 18:11:49 2015
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
......@@ -113,16 +113,12 @@
#define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
/* definitions for field: Reserved in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_MASK WBGEN2_GEN_MASK(6, 26)
#define ACQ_CORE_TRIG_CFG_RESERVED_SHIFT 6
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 10)
#define ACQ_CORE_TRIG_CFG_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 6, 26)
#define ACQ_CORE_TRIG_CFG_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 6, 26)
/* definitions for field: Threshold for internal trigger in reg: Trigger configuration */
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_MASK WBGEN2_GEN_MASK(16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_SHIFT 16
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Trigger data threshold */
/* definitions for register: Trigger delay */
......@@ -152,6 +148,8 @@
/* definitions for register: DDR3 Start Address */
/* definitions for register: DDR3 End Address */
/* definitions for register: Acquisition channel control */
/* definitions for field: Acquisition channel selection in reg: Acquisition channel control */
......@@ -159,32 +157,32 @@
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_SHIFT 0
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define ACQ_CORE_ACQ_CHAN_CTL_WHICH_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
PACKED struct ACQ_CORE_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
/* [0x4]: REG Status register */
uint32_t STA;
/* [0x8]: REG Trigger configuration */
uint32_t TRIG_CFG;
/* [0xc]: REG Trigger delay */
uint32_t TRIG_DLY;
/* [0x10]: REG Software trigger */
uint32_t SW_TRIG;
/* [0x14]: REG Number of shots */
uint32_t SHOTS;
/* [0x18]: REG Trigger address register */
uint32_t TRIG_POS;
/* [0x1c]: REG Pre-trigger samples */
uint32_t PRE_SAMPLES;
/* [0x20]: REG Post-trigger samples */
uint32_t POST_SAMPLES;
/* [0x24]: REG Samples counter */
uint32_t SAMPLES_CNT;
/* [0x28]: REG DDR3 Start Address */
uint32_t DDR3_START_ADDR;
/* [0x2c]: REG Acquisition channel control */
uint32_t ACQ_CHAN_CTL;
};
/* [0x0]: REG Control register */
#define ACQ_CORE_REG_CTL 0x00000000
/* [0x4]: REG Status register */
#define ACQ_CORE_REG_STA 0x00000004
/* [0x8]: REG Trigger configuration */
#define ACQ_CORE_REG_TRIG_CFG 0x00000008
/* [0xc]: REG Trigger data threshold */
#define ACQ_CORE_REG_TRIG_DATA_THRES 0x0000000c
/* [0x10]: REG Trigger delay */
#define ACQ_CORE_REG_TRIG_DLY 0x00000010
/* [0x14]: REG Software trigger */
#define ACQ_CORE_REG_SW_TRIG 0x00000014
/* [0x18]: REG Number of shots */
#define ACQ_CORE_REG_SHOTS 0x00000018
/* [0x1c]: REG Trigger address register */
#define ACQ_CORE_REG_TRIG_POS 0x0000001c
/* [0x20]: REG Pre-trigger samples */
#define ACQ_CORE_REG_PRE_SAMPLES 0x00000020
/* [0x24]: REG Post-trigger samples */
#define ACQ_CORE_REG_POST_SAMPLES 0x00000024
/* [0x28]: REG Samples counter */
#define ACQ_CORE_REG_SAMPLES_CNT 0x00000028
/* [0x2c]: REG DDR3 Start Address */
#define ACQ_CORE_REG_DDR3_START_ADDR 0x0000002c
/* [0x30]: REG DDR3 End Address */
#define ACQ_CORE_REG_DDR3_END_ADDR 0x00000030
/* [0x34]: REG Acquisition channel control */
#define ACQ_CORE_REG_ACQ_CHAN_CTL 0x00000034
#endif
hdl/sim/regs/wb_acq_core_regs.vh
View file @ ad0c3a74
......@@ -38,21 +38,21 @@
`define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL_OFFSET 4
`define ACQ_CORE_TRIG_CFG_INT_TRIG_SEL 32'h00000030
`define ACQ_CORE_TRIG_CFG_RESERVED_OFFSET 6
`define ACQ_CORE_TRIG_CFG_RESERVED 32'h0000ffc0
`define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES_OFFSET 16
`define ACQ_CORE_TRIG_CFG_INT_TRIG_THRES 32'hffff0000
`define ADDR_ACQ_CORE_TRIG_DLY 6'hc
`define ADDR_ACQ_CORE_SW_TRIG 6'h10
`define ADDR_ACQ_CORE_SHOTS 6'h14
`define ACQ_CORE_TRIG_CFG_RESERVED 32'hffffffc0
`define ADDR_ACQ_CORE_TRIG_DATA_THRES 6'hc
`define ADDR_ACQ_CORE_TRIG_DLY 6'h10
`define ADDR_ACQ_CORE_SW_TRIG 6'h14
`define ADDR_ACQ_CORE_SHOTS 6'h18
`define ACQ_CORE_SHOTS_NB_OFFSET 0
`define ACQ_CORE_SHOTS_NB 32'h0000ffff
`define ACQ_CORE_SHOTS_RESERVED_OFFSET 16
`define ACQ_CORE_SHOTS_RESERVED 32'hffff0000
`define ADDR_ACQ_CORE_TRIG_POS 6'h18
`define ADDR_ACQ_CORE_PRE_SAMPLES 6'h1c
`define ADDR_ACQ_CORE_POST_SAMPLES 6'h20
`define ADDR_ACQ_CORE_SAMPLES_CNT 6'h24
`define ADDR_ACQ_CORE_DDR3_START_ADDR 6'h28
`define ADDR_ACQ_CORE_ACQ_CHAN_CTL 6'h2c
`define ADDR_ACQ_CORE_TRIG_POS 6'h1c
`define ADDR_ACQ_CORE_PRE_SAMPLES 6'h20
`define ADDR_ACQ_CORE_POST_SAMPLES 6'h24
`define ADDR_ACQ_CORE_SAMPLES_CNT 6'h28
`define ADDR_ACQ_CORE_DDR3_START_ADDR 6'h2c
`define ADDR_ACQ_CORE_DDR3_END_ADDR 6'h30
`define ADDR_ACQ_CORE_ACQ_CHAN_CTL 6'h34
`define ACQ_CORE_ACQ_CHAN_CTL_WHICH_OFFSET 0
`define ACQ_CORE_ACQ_CHAN_CTL_WHICH 32'h0000001f
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