This signal was being used as input into a Wishbone
register, as as a loopback to top design (so one
can probe this signal, if desired). However, on
refactoring the active_clk module, the loopback
signal fmc_pll_status_o was being driven by 2
nets: the loopback in the outer FMC module,
the internal loopback inside the active_clk
module.

This made the synthesis tool confused and
optimized away the Wishbone register signal.

This fixes #66 github issue.