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Beam Positoning Monitor - Gateware
Commit 28d21f3a authored by Lucas Russo's avatar Lucas Russo
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wb_fmc250m_4ch,wb_fmc130m_4ch: fix unconnected pll_status signal 

This signal was being used as input into a Wishbone
register, as as a loopback to top design (so one
can probe this signal, if desired). However, on
refactoring the active_clk module, the loopback
signal fmc_pll_status_o was being driven by 2
nets: the loopback in the outer FMC module,
the internal loopback inside the active_clk
module.

This made the synthesis tool confused and
optimized away the Wishbone register signal.

This fixes #66 github issue.
parent bc9cf982
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hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ 28d21f3a
......@@ -562,12 +562,6 @@ begin
end generate;
end generate;
-----------------------------
-- General status board pins
-----------------------------
-- PLL status available through a regular core pin
fmc_pll_status_o <= fmc_pll_status_i;
-----------------------------
-- Insert extra Wishbone registering stage for ease timing.
-- It effectively cuts the bandwodth in half!
......
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @ 28d21f3a
......@@ -575,12 +575,6 @@ begin
end generate;
end generate;
-----------------------------
-- General status board pins
-----------------------------
-- PLL status available through a regular core pin
fmc_pll_status_o <= fmc_pll_status_i;
-----------------------------
-- Insert extra Wishbone registering stage for ease timing.
-- It effectively cuts the bandwidth in half!
......
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