There's a bug in Vivado: when AXI ID port width is set e.g. to 4,
and user connects "0000" vector to these ports it will result in implementation error.
Therefore, it's necessary to reconfigure IP core to change this parameter.
But this causes width change of all ID ports and signals.
This means that it's impossible to build standalone PCIe project right after git checkout.
Make life a bit easier for anyone who wishes this.