Skip to content

B
Beam Positoning Monitor - Gateware
Commit 66777cb9 authored by Adrian Byszuk (CTI)'s avatar Adrian Byszuk (CTI)
Browse files
Options

PCIe/DDR: make it easier to change AXI ID width 

There's a bug in Vivado: when AXI ID port width is set e.g. to 4,
and user connects "0000" vector to these ports it will result in implementation error.
Therefore, it's necessary to reconfigure IP core to change this parameter.
But this causes width change of all ID ports and signals.
This means that it's impossible to build standalone PCIe project right after git checkout.
Make life a bit easier for anyone who wishes this.
parent 9457f6a6
Hide whitespace changes
Inline Side-by-side
Showing with 22 additions and 14 deletions
hdl/modules/pcie/common/ddr_Transact.vhd
View file @ 66777cb9
......@@ -172,7 +172,7 @@ PORT MAP (
INTERCONNECT_ARESETN => irconnect_arstn,
S00_AXI_ARESET_OUT_N => pcie_axi_aresetn,
S00_AXI_ACLK => pcie_clk,
S00_AXI_AWID => "0000",
S00_AXI_AWID => (C_AXI_SLAVE_TID_WIDTH-1 downto 0 => '0'),
S00_AXI_AWADDR => pcie_axi_awaddr,
S00_AXI_AWLEN => pcie_axi_awlen,
S00_AXI_AWSIZE => pcie_axi_awsize,
......@@ -192,7 +192,7 @@ PORT MAP (
S00_AXI_BRESP => pcie_axi_bresp,
S00_AXI_BVALID => pcie_axi_bvalid,
S00_AXI_BREADY => pcie_axi_bready,
S00_AXI_ARID => "0000",
S00_AXI_ARID => (C_AXI_SLAVE_TID_WIDTH-1 downto 0 => '0'),
S00_AXI_ARADDR => pcie_axi_araddr,
S00_AXI_ARLEN => pcie_axi_arlen,
S00_AXI_ARSIZE => pcie_axi_arsize,
......@@ -211,7 +211,7 @@ PORT MAP (
S00_AXI_RREADY => pcie_axi_rready,
S01_AXI_ARESET_OUT_N => s_axi_aresetn_out,
S01_AXI_ACLK => ddr_ui_clk,
S01_AXI_AWID => s_axi_awid,
S01_AXI_AWID => s_axi_awid(C_AXI_SLAVE_TID_WIDTH-1 downto 0),
S01_AXI_AWADDR => s_axi_awaddr,
S01_AXI_AWLEN => s_axi_awlen,
S01_AXI_AWSIZE => s_axi_awsize,
......@@ -227,11 +227,11 @@ PORT MAP (
S01_AXI_WLAST => s_axi_wlast,
S01_AXI_WVALID => s_axi_wvalid,
S01_AXI_WREADY => s_axi_wready,
S01_AXI_BID => s_axi_bid,
S01_AXI_BID => s_axi_bid(C_AXI_SLAVE_TID_WIDTH-1 downto 0),
S01_AXI_BRESP => s_axi_bresp,
S01_AXI_BVALID => s_axi_bvalid,
S01_AXI_BREADY => s_axi_bready,
S01_AXI_ARID => s_axi_arid,
S01_AXI_ARID => s_axi_arid(C_AXI_SLAVE_TID_WIDTH-1 downto 0),
S01_AXI_ARADDR => s_axi_araddr,
S01_AXI_ARLEN => s_axi_arlen,
S01_AXI_ARSIZE => s_axi_arsize,
......@@ -242,7 +242,7 @@ PORT MAP (
S01_AXI_ARQOS => s_axi_arqos,
S01_AXI_ARVALID => s_axi_arvalid,
S01_AXI_ARREADY => s_axi_arready,
S01_AXI_RID => s_axi_rid,
S01_AXI_RID => s_axi_rid(C_AXI_SLAVE_TID_WIDTH-1 downto 0),
S01_AXI_RDATA => s_axi_rdata,
S01_AXI_RRESP => s_axi_rresp,
S01_AXI_RLAST => s_axi_rlast,
......@@ -250,7 +250,7 @@ PORT MAP (
S01_AXI_RREADY => s_axi_rready,
M00_AXI_ARESET_OUT_N => ddr_axi_aresetn,
M00_AXI_ACLK => ddr_ui_clk,
M00_AXI_AWID => ddr_axi_awid,
M00_AXI_AWID => ddr_axi_awid(C_DDR_TID_WIDTH-1 downto 0),
M00_AXI_AWADDR => ddr_axi_awaddr,
M00_AXI_AWLEN => ddr_axi_awlen,
M00_AXI_AWSIZE => ddr_axi_awsize,
......@@ -266,11 +266,11 @@ PORT MAP (
M00_AXI_WLAST => ddr_axi_wlast,
M00_AXI_WVALID => ddr_axi_wvalid,
M00_AXI_WREADY => ddr_axi_wready,
M00_AXI_BID => ddr_axi_bid,
M00_AXI_BID => ddr_axi_bid(C_DDR_TID_WIDTH-1 downto 0),
M00_AXI_BRESP => ddr_axi_bresp,
M00_AXI_BVALID => ddr_axi_bvalid,
M00_AXI_BREADY => ddr_axi_bready,
M00_AXI_ARID => ddr_axi_arid,
M00_AXI_ARID => ddr_axi_arid(C_DDR_TID_WIDTH-1 downto 0),
M00_AXI_ARADDR => ddr_axi_araddr,
M00_AXI_ARLEN => ddr_axi_arlen,
M00_AXI_ARSIZE => ddr_axi_arsize,
......@@ -281,7 +281,7 @@ PORT MAP (
M00_AXI_ARQOS => ddr_axi_arqos,
M00_AXI_ARVALID => ddr_axi_arvalid,
M00_AXI_ARREADY => ddr_axi_arready,
M00_AXI_RID => ddr_axi_rid,
M00_AXI_RID => ddr_axi_rid(C_DDR_TID_WIDTH-1 downto 0),
M00_AXI_RDATA => ddr_axi_rdata,
M00_AXI_RRESP => ddr_axi_rresp,
M00_AXI_RLAST => ddr_axi_rlast,
......@@ -397,7 +397,7 @@ begin
app_ref_ack => open,
app_zq_ack => open,
-- Slave Interface Write Address Ports
s_axi_awid => ddr_axi_awid,
s_axi_awid => ddr_axi_awid(C_DDR_TID_WIDTH-1 downto 0),
s_axi_awaddr => ddr_axi_awaddr(c_ddr_addr_width-1 downto 0),
s_axi_awlen => ddr_axi_awlen,
s_axi_awsize => ddr_axi_awsize,
......@@ -415,12 +415,12 @@ begin
s_axi_wvalid => ddr_axi_wvalid,
s_axi_wready => ddr_axi_wready,
-- Slave Interface Write Response Ports
s_axi_bid => ddr_axi_bid,
s_axi_bid => ddr_axi_bid(C_DDR_TID_WIDTH-1 downto 0),
s_axi_bresp => ddr_axi_bresp,
s_axi_bvalid => ddr_axi_bvalid,
s_axi_bready => ddr_axi_bready,
-- Slave Interface Read Address Ports
s_axi_arid => ddr_axi_arid,
s_axi_arid => ddr_axi_arid(C_DDR_TID_WIDTH-1 downto 0),
s_axi_araddr => ddr_axi_araddr(c_ddr_addr_width-1 downto 0),
s_axi_arlen => ddr_axi_arlen,
s_axi_arsize => ddr_axi_arsize,
......@@ -432,7 +432,7 @@ begin
s_axi_arvalid => ddr_axi_arvalid,
s_axi_arready => ddr_axi_arready,
-- Slave Interface Read Data Ports
s_axi_rid => ddr_axi_rid,
s_axi_rid => ddr_axi_rid(C_DDR_TID_WIDTH-1 downto 0),
s_axi_rdata => ddr_axi_rdata,
s_axi_rresp => ddr_axi_rresp,
s_axi_rlast => ddr_axi_rlast,
......
hdl/platform/artix7/afc_v3/ipcores_pkg.vhd
View file @ 66777cb9
......@@ -19,6 +19,8 @@ constant C_DDR_CKE_WIDTH : positive := 1;
constant C_DDR_ODT_WIDTH : positive := 1;
constant C_DDR_ADDR_WIDTH : positive := 31;
constant C_DDR_TID_WIDTH : positive := 8;
constant C_AXI_SLAVE_TID_WIDTH : positive := 4;
--***************************************************************************
-- Necessary parameters for AXI BPM Data Mover core support
-- (dependent on generated core, not to be modified at will)
......
hdl/platform/kintex7/afck/ipcores_pkg.vhd
View file @ 66777cb9
......@@ -19,6 +19,9 @@ constant C_DDR_CKE_WIDTH : positive := 1;
constant C_DDR_ODT_WIDTH : positive := 1;
constant C_DDR_ADDR_WIDTH : positive := 31;
constant C_DDR_TID_WIDTH : positive := 8;
constant C_AXI_SLAVE_TID_WIDTH : positive := 4;
-- ----------------------------------------------------------------------------
-- Component declarations
-- ----------------------------------------------------------------------------
......
hdl/platform/kintex7/kc705/ipcores_pkg.vhd
View file @ 66777cb9
......@@ -19,6 +19,9 @@ constant C_DDR_CKE_WIDTH : positive := 1;
constant C_DDR_ODT_WIDTH : positive := 1;
constant C_DDR_ADDR_WIDTH : positive := 30;
constant C_DDR_TID_WIDTH : positive := 8;
constant C_AXI_SLAVE_TID_WIDTH : positive := 4;
-- ----------------------------------------------------------------------------
-- Component declarations
-- ----------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment