reset_synch: add missing rst signal to sensitivity list

00012c2d · Lucas Russo · 7cd84815 · 00012c2d
Commit 00012c2d authored Nov 16, 2016 by Lucas Russo
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reset_synch.vhd hdl/modules/dbe_common/reset_synch/reset_synch.vhd +1 -1

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--- a/hdl/modules/dbe_common/reset_synch/reset_synch.vhd
+++ b/hdl/modules/dbe_common/reset_synch/reset_synch.vhd
@@ -50,7 +50,7 @@ begin

  gen_pipe : if g_pipeline > 1 generate
    -- Shift reg
-    p_rst_pipe : process (clk_i)
+    p_rst_pipe : process (clk_i, arst_n_i)
    begin
      if arst_n_i = '0' then
        for i in 0 to g_pipeline-2 loop