hdl/testbench/*/wb_acq_core_test/*: add instructions on README

There is an error when simulating the RS232 module with modelsim. For now, it is safe to exclude the file from the Manifest file (see README), as we do not use it in simulation.

hdl/testbench//wb_acq_core_test/: add instructions on README
There is an error when simulating the RS232 module with modelsim. For now, it is safe to exclude the file from the Manifest file (see README), as we do not use it in simulation.
13bd7cb9 · Lucas Russo · fccdaf12 · 13bd7cb9
Commit 13bd7cb9 authored Jan 14, 2014 by Lucas Russo
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README hdl/testbench/wishbone/wb_acq_core_test/verilog/README +6 -0

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/README
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/README
+WARNING!     WARNING!    WARNING!    WARNING!
+
+You should comment the rs232 module from the Manifest
+located in "hdl/modules/dbe_wishbone/Manifest.py"
+as modelsim is not appeased with some concatenation.
+The error does not appears in synthesis (Xst).