Revert "modules/*/wb_acq_core/*: safer DDR start/end registers rst/wrapping"

This reverts commit 8c69f3bf. For fast acquisition paths (e.g., ADC, ADCSWAP), this would cause error on long-running acquisitions (i.e., hw or sw trigger). This is probably related to the fact that the DDR end address might not be correctly configured after a reset. We must properly understand the issue (FIXME).

Revert "modules//wb_acq_core/: safer DDR start/end registers rst/wrapping"
This reverts commit 8c69f3bf. For fast acquisition paths (e.g., ADC, ADCSWAP), this would cause error on long-running acquisitions (i.e., hw or sw trigger). This is probably related to the fact that the DDR end address might not be correctly configured after a reset. We must properly understand the issue (FIXME).
189d2cde · Lucas Russo · 8c69f3bf · 189d2cde
Commit 189d2cde authored Jun 03, 2016 by Lucas Russo
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acq_ddr3_axis_write.vhd hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd +5 -3

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--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_write.vhd
@@ -518,8 +518,10 @@ begin
    if rising_edge(ext_clk_i) then
      if ext_rst_n_i = '0' then
        ddr_addr_cnt_axis <= to_unsigned(0, ddr_addr_cnt_axis'length);
-        ddr_addr_init <= to_unsigned(0, ddr_addr_init'length);
-        ddr_addr_max <= to_unsigned(0, ddr_addr_max'length);
+        -- FIXME: Reset the init/end register cause fast acquisition
+        -- data path to fail on hw or sw trigger acquisitions.
+        -- This might be related to the fact that these addresses
+        -- might not be properly configured.
      else

        if wr_start_i = '1' then
@@ -533,7 +535,7 @@ begin
          -- Get ready for the next valid transaction
          ddr_addr_cnt_axis <= ddr_addr_cnt_axis + c_addr_ddr_inc_axis;
          -- Wrap counters if we go over the limit
-          if ddr_addr_cnt_axis >= ddr_addr_max then
+          if ddr_addr_cnt_axis = ddr_addr_max then
            ddr_addr_cnt_axis <= ddr_addr_init;
          end if;
        end if;