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Beam Positoning Monitor - Gateware
Commit 1a22d679 authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/*: add remaining onewire and i2c interfaces

parent d54d119d
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Showing with 288 additions and 115 deletions
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
View file @ 1a22d679
...@@ -414,13 +414,13 @@ package custom_wishbone_pkg is ...@@ -414,13 +414,13 @@ package custom_wishbone_pkg is
-- SPI interface? -- SPI interface?
lmk_lock_i : in std_logic; lmk_lock_i : in std_logic;
lmk_sync_o : out std_logic; lmk_sync_o : out std_logic;
lmk_latch_en_o : out std_logic; lmk_uwire_latch_en_o : out std_logic;
lmk_data_o : out std_logic; lmk_uwire_data_o : out std_logic;
lmk_clock_o : out std_logic; lmk_uwire_clock_o : out std_logic;
-- Programable VCXO via I2C? -- Programable VCXO via I2C?
vcxo_sda_b : inout std_logic; vcxo_i2c_sda_b : inout std_logic;
vcxo_scl_o : out std_logic; vcxo_i2c_scl_o : out std_logic;
vcxo_pd_l_o : out std_logic; vcxo_pd_l_o : out std_logic;
-- One-wire To/From DS2431 (VMETRO Data) -- One-wire To/From DS2431 (VMETRO Data)
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ 1a22d679
...@@ -26,8 +26,8 @@ use unisim.vcomponents.all; ...@@ -26,8 +26,8 @@ use unisim.vcomponents.all;
entity fmc516_adc_clk is entity fmc516_adc_clk is
generic generic
( (
-- This genric must be specified -- This generic must be specified
g_adc_clock_period : real; g_adc_clock_period : real := 10.00;
g_default_adc_clk_delay : natural := 0; g_default_adc_clk_delay : natural := 0;
g_sim : integer := 0 g_sim : integer := 0
); );
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_iface.vhd
View file @ 1a22d679
...@@ -182,7 +182,7 @@ architecture rtl of fmc516_adc_iface is ...@@ -182,7 +182,7 @@ architecture rtl of fmc516_adc_iface is
component fmc516_adc_clk component fmc516_adc_clk
generic( generic(
-- This genric must be specified -- This genric must be specified
g_adc_clock_period : real; g_adc_clock_period : real := 10.00;
g_default_adc_clk_delay : natural := 0; g_default_adc_clk_delay : natural := 0;
g_sim : integer := 0 g_sim : integer := 0
); );
......
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