hdl/modules/fmc_adc_common/fmc_adc_data.vhd: add reset to FIFO

As of now, we are using an updated version of the general-cores repository. One of the modifications is the absence of the coregen stuff used for generating FIFOs and RAMs. Now, Xilinx primitives are used for that and a wrapper is provided to customize it.

hdl/modules/fmc_adc_common/fmc_adc_data.vhd: add reset to FIFO
As of now, we are using an updated version of the general-cores repository. One of the modifications is the absence of the coregen stuff used for generating FIFOs and RAMs. Now, Xilinx primitives are used for that and a wrapper is provided to customize it.
1db36dc9 · Lucas Russo · 88629f07 · 1db36dc9
Commit 1db36dc9 authored Jan 23, 2014 by Lucas Russo
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fmc_adc_data.vhd hdl/modules/fmc_adc_common/fmc_adc_data.vhd +1 -3

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--- a/hdl/modules/fmc_adc_common/fmc_adc_data.vhd
+++ b/hdl/modules/fmc_adc_common/fmc_adc_data.vhd
@@ -339,9 +339,7 @@ begin
    g_size                                => async_fifo_size
  )
  port map(
-    --rst_n_i                               => sys_rst_n_i,
-    -- We don't need this reset as this FIFO is used for CDC only
-    rst_n_i                               => '1',
+    rst_n_i                               => sys_rst_n_i,

    -- write port
    clk_wr_i                              => adc_clk_bufr,