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Beam Positoning Monitor - Gateware
Commit 20213a7b authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: add spi delay and other tests on main

parent f2537dd9
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Showing with 2234 additions and 2128 deletions
embedded-sw/dbe.vhd
View file @ 20213a7b
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embedded-sw/dbe_main.c
View file @ 20213a7b
......@@ -367,12 +367,27 @@ void fmc516_test()
pp_printf("> FMC516 ADCs info...\n");
//pp_printf("> FMC516 ADCs resetting...\n");
//delay(LED_DELAY);
//fmc516_reset_adcs(FMC516_ID);
//delay(LED_DELAY);
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d calibration progress...\n", i);
while(!(fmc516_isla216_chkcal_stat(i)));
pp_printf("done\n");
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// pp_printf("> FMC516_ISLA216_ADC%d port_config: %d\n",
// i, fmc516_isla216_read_byte(0x00, i));
//}
//
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// pp_printf("> FMC516_ISLA216_ADC%d user_pat: %d\n",
// i, fmc516_isla216_read_byte(0xC1, i));
//}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d chip id: %d\n",
i, fmc516_isla216_get_chipid(i));
......@@ -380,14 +395,77 @@ void fmc516_test()
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d chip version: %d\n",
i, fmc516_isla216_get_chipver(FMC516_ISLA216_ADC0));
i, fmc516_isla216_get_chipver(i));
}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
pp_printf("> FMC516_ISLA216_ADC%d test mode off\n", i);
fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_OFF),
ISLA216_TESTIO_REG, i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_ramp(i);
// pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
//}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_midscale(i);
// pp_printf("> FMC516_ISLA216_ADC%d: test miscale enabled!\n", i);
//}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
fmc516_isla216_test_ramp(i);
pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
pp_printf("> FMC516_ISLA216_ADC%d: testio reg: 0X%8X\n", i,
fmc516_isla216_read_byte(ISLA216_TESTIO_REG, i));
}
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
delay(LED_DELAY+32);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
delay(LED_DELAY+124);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
delay(LED_DELAY+1);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
delay(LED_DELAY);
pp_printf("> ADC data0 %d\n", fmc516_read_adc0(0));
delay(LED_DELAY+12384);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
delay(LED_DELAY+32);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
delay(LED_DELAY+124);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
delay(LED_DELAY+1);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
delay(LED_DELAY);
pp_printf("> ADC data1 %d\n", fmc516_read_adc1(0));
delay(LED_DELAY+12384);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY+32);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY+124);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY+1);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY);
pp_printf("> ADC data2 %d\n", fmc516_read_adc2(0));
delay(LED_DELAY+12384);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY+32);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY+124);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY+1);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY);
pp_printf("> ADC data3 %d\n", fmc516_read_adc3(0));
delay(LED_DELAY+12384);
dbg_print("> initilizing fmc516 delays\n");
fmc516_init_delays(0);
pp_printf("> test finished...\n");
}
......
embedded-sw/dev/spi.c
View file @ 20213a7b
......@@ -8,7 +8,7 @@
#include "memmgr.h" // malloc and free clones
#include "debug_print.h"
#define SPI_DELAY 50
#define SPI_DELAY 300
// Global SPI handler.
spi_t **spi;
......@@ -34,7 +34,7 @@ int spi_init(void)
// Default configuration
spi[i]->DIVIDER = DEFAULT_SPI_DIVIDER & SPI_DIV_MASK;
spi_config[i] = SPI_CTRL_ASS | SPI_CTRL_TXNEG;
//spi[i]->CTRL = spi_config[i];
spi[i]->CTRL = spi_config[i];
dbg_print("> spi addr[%d]: %08X\n", i, spi[i]);
dbg_print("> spi rx0 addr[%d]: %08X\n", i, &spi[i]->RX0);
dbg_print("> spi tx0 addr[%d]: %08X\n", i, &spi[i]->TX0);
......@@ -53,6 +53,7 @@ int spi_init(void)
dbg_print("> spi ctrl_txneg: %08X\n", spi[i]->CTRL & SPI_CTRL_TXNEG);
dbg_print("> spi ctrl_lsb: %08X\n", spi[i]->CTRL & SPI_CTRL_LSB);
dbg_print("> spi ctrl_dir: %08X\n", spi[i]->CTRL & SPI_CTRL_DIR);
dbg_print("> spi ctrl_three_mode: %08X\n", spi[i]->CTRL & SPI_CTRL_THREE_WIRE);
}
//spi = (spi_t *)spi_devl->devices->base;;
return 0;
......@@ -98,12 +99,17 @@ void oc_spi_config(unsigned int id, int ass, int rx_neg, int tx_neg,
// For use only with spi three-wire mode
int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
{
dbg_print(">oc_spi_three_mode_tx...\n");
dbg_print("> oc_spi_three_mode_tx...\n");
// Write configuration to SPI core. SPI_CTRL_DIR = 1
spi[id]->CTRL = spi_config[id] | SPI_CTRL_DIR | SPI_CTRL_CHAR_LEN(nbits);
// Transmit to core
spi[id]->TX0 = in;
//spi[id]->TX1 = 0;
//spi[id]->TX2 = 0;
//spi[id]->TX3 = 0;
dbg_print("> spi[id]->TX0: 0x%8X\n", spi[id]->TX0);
dbg_print("> spi[id]->RX0: 0x%8X\n", spi[id]->RX0);
spi[id]->SS = (1 << ss);
......@@ -111,31 +117,51 @@ int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
// Wait for completion
dbg_print(">oc_spi_three_mode_tx: waiting to spi...\n");
dbg_print("> oc_spi_three_mode_tx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
delay(SPI_DELAY);
dbg_print("> spi[id]->TX0: 0x%8X\n", spi[id]->TX0);
dbg_print("> spi[id]->RX0: 0x%8X\n", spi[id]->RX0);
return 0;
}
// For use only with spi three-wire mode
int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
{
dbg_print(">oc_spi_three_mode_rx...\n");
dbg_print("> oc_spi_three_mode_rx...\n");
// Write configuration to SPI core. SPI_CTRL_DIR = 0
spi[id]->CTRL = spi_config[id] | SPI_CTRL_CHAR_LEN(nbits);
spi[id]->SS = (1 << ss);
// TEST ONLY
spi[id]->RX0 = 0;
//spi[id]->RX1 = 0;
//spi[id]->RX2 = 0;
//spi[id]->RX3 = 0;
dbg_print("> spi[id]->TX0: 0x%8X\n", spi[id]->TX0);
dbg_print("> spi[id]->RX0: 0x%8X\n", spi[id]->RX0);
// Initiate transaction
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
// Wait for reception
dbg_print(">oc_spi_three_mode_rx: waiting to spi...\n");
dbg_print("> oc_spi_three_mode_rx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
delay(SPI_DELAY);
dbg_print("> spi[id]->TX0: 0x%8X\n", spi[id]->TX0);
dbg_print("> spi[id]->RX0: 0x%8X\n", spi[id]->RX0);
*out = spi[id]->RX0;
dbg_print("> *out: 0x%8X\n", *out);
return 0;
}
......@@ -143,7 +169,7 @@ int oc_spi_txrx(unsigned int id, int ss, int nbits, uint32_t in, uint32_t *out)
{
uint32_t rval;
dbg_print(">oc_spi_txrx...\n");
dbg_print("> oc_spi_txrx...\n");
// Avoid breaking the code when just issuing a read command (out can be null)
if (!out)
out = &rval;
......@@ -158,7 +184,7 @@ int oc_spi_txrx(unsigned int id, int ss, int nbits, uint32_t in, uint32_t *out)
spi[id]->SS = (1 << ss);
spi[id]->CTRL |= SPI_CTRL_GO_BSY;
dbg_print(">oc_spi_txrx: waiting to spi...\n");
dbg_print("> oc_spi_txrx: waiting to spi...\n");
while(oc_spi_poll(id))
delay(SPI_DELAY);
......
embedded-sw/include/hw/wb_spi.h
View file @ 20213a7b
......@@ -32,31 +32,32 @@
#define SPI_CTRL_GO_BSY (1<<8)
#define SPI_CTRL_BSY (1<<8)
#define SPI_CTRL_CHAR_LEN(x) ((x) & 0x7f)
#define SPI_CTRL_SS(x) ((x) & 0xff)
#define SPI_LGH_MASK 0x7F
#define SPI_DIV_MASK 0xFFFF
PACKED struct SPI_WB {
union {
uint32_t RX0;
uint32_t TX0;
};
union {
uint32_t RX1;
uint32_t TX1;
};
union {
uint32_t RX2;
uint32_t TX2;
};
union {
uint32_t RX3;
uint32_t TX3;
};
uint32_t CTRL;
uint32_t DIVIDER;
uint32_t SS;
union {
uint32_t RX0;
uint32_t TX0;
};
union {
uint32_t RX1;
uint32_t TX1;
};
union {
uint32_t RX2;
uint32_t TX2;
};
union {
uint32_t RX3;
uint32_t TX3;
};
uint32_t CTRL;
uint32_t DIVIDER;
uint32_t SS;
};
#endif
embedded-sw/include/spi.h
View file @ 20213a7b
......@@ -7,7 +7,8 @@
/*
* fsclk = fs_wbclk / (divider+1)*2
*/
#define DEFAULT_SPI_DIVIDER 100
#define DEFAULT_SPI_DIVIDER 99
//#define DEFAULT_SPI_DIVIDER 9
/* Type definitions */
typedef volatile struct SPI_WB spi_t;
......
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