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Beam Positoning Monitor - Gateware
Commit 230d9e1e authored by Adrian Byszuk's avatar Adrian Byszuk
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Update design files to regenerated PCIe core

parent 078cbb3c
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Showing with 83 additions and 82 deletions
hdl/syn/pcie/bpm_pcie_k7.xise
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...@@ -89,7 +89,7 @@ ...@@ -89,7 +89,7 @@
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
...@@ -109,7 +109,7 @@ ...@@ -109,7 +109,7 @@
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Clock Region Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -148,10 +148,13 @@ ...@@ -148,10 +148,13 @@
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -213,6 +216,7 @@ ...@@ -213,6 +216,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
...@@ -307,6 +311,7 @@ ...@@ -307,6 +311,7 @@
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -315,7 +320,7 @@ ...@@ -315,7 +320,7 @@
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
...@@ -338,198 +343,195 @@ ...@@ -338,198 +343,195 @@
<libraries/> <libraries/>
<files> <files>
<file xil_pn:name="../../top/pcie/bpm_pcie_k7.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="xc7k325ffg900.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/bram_x64.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../top/pcie/bpm_pcie_k7.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/eb_fifo_counted_resized.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/bram_x64.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/mbuf_128x72.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/eb_fifo_counted_resized.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/prime_FIFO_plain.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/mbuf_128x72.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/sfifo_15x128.ngc" xil_pn:type="FILE_NGC"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/prime_FIFO_plain.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/v6abb64Package_efifo_elink.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/sfifo_15x128.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/DDR_Blinker.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/v6abb64Package_efifo_elink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/DMA_Calculate.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/DDR_Blinker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/DMA_FSM.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/DMA_Calculate.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/FF_tagram64x36.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/DMA_FSM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/FIFO_Wrapper.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/FF_tagram64x36.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/FIFO_Wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/Interrupts.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/FIFO_Wrapper_Loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/PCIe_UserLogic_00.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/Interrupts.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/Registers.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/PCIe_UserLogic_00.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/RxIn_Delays.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/Registers.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/Tx_Output_Arbitor.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/RxIn_Delays.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/bram_DDRs_Control.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/Tx_Output_Arbitor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/bram_DDRs_Control_Loopback.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/bram_DDRs_Control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_CplD_Channel.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/bram_DDRs_Control_Loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_MRd_Channel.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_CplD_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_MWr_Channel.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_MRd_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_Transact.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_MWr_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_dsDMA_Channel.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_Transact.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/rx_usDMA_Channel.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_dsDMA_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/tlpControl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/rx_usDMA_Channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/tx_Mem_Reader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/tlpControl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../../modules/pcie/common/tx_Transact.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/pcie/common/tx_Mem_Reader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../modules/pcie/common/tx_Transact.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_lane.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_pipeline.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_drp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_thrtl_ctl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_lane.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_user.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/> <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/> <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx_thrtl_ctl.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_reset.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_null_gen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/> <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_brams_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/> <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_sync.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/> <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx_pipeline.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_user.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_drp.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/> <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_rx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_reset.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/> <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_7x.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_axi_basic_tx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/> <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_pipeline.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/> <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_fast_cfg_init_cntr.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gtp_pipe_reset.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/> <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_drp.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_clock.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/> <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_top_7x.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_qpll_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/> <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_pipe_misc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/> <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/> <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_rxeq_scan.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_wrapper.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/> <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_gt_rx_valid_filter_7x.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_rate.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/> <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file> </file>
<file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pcie_bram_7x.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/> <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file> </file>
<file xil_pn:name="xc7k325ffg900.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
</files> </files>
<bindings/> <bindings/>
......
hdl/syn/pcie/xc7k325ffg900.ucf
View file @ 230d9e1e
...@@ -104,14 +104,14 @@ INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i" LOC = PCIE_X0Y0; ...@@ -104,14 +104,14 @@ INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i" LOC = PCIE_X0Y0;
# #
# BlockRAM placement # BlockRAM placement
# #
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X5Y35; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X5Y35;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y36; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y36;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y35; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y35;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y34; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y34;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y33; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y33;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y32; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y32;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y31; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y31;
INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/ramb_bl.ramb36_dp_bl.ram36_bl" LOC = RAMB36_X4Y30; INST "pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X4Y30;
############################################################################### ###############################################################################
# Timing Constraints # Timing Constraints
############################################################################### ###############################################################################
......
hdl/top/pcie/bpm_pcie_k7.vhd
View file @ 230d9e1e
...@@ -303,7 +303,7 @@ architecture Behavioral of bpm_pcie_k7 is ...@@ -303,7 +303,7 @@ architecture Behavioral of bpm_pcie_k7 is
-- 8. System(SYS) Interface -- -- 8. System(SYS) Interface --
------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------
sys_clk : in std_logic; sys_clk : in std_logic;
sys_reset : in std_logic); sys_rst_n : in std_logic);
end component; end component;
component PCIe_UserLogic_00 component PCIe_UserLogic_00
...@@ -1344,8 +1344,7 @@ begin ...@@ -1344,8 +1344,7 @@ begin
-- RX -- RX
m_axis_rx_tdata => m_axis_rx_tdata , m_axis_rx_tdata => m_axis_rx_tdata ,
m_axis_rx_tkeep(0) => m_axis_rx_tkeep(0) , m_axis_rx_tkeep => m_axis_rx_tkeep ,
m_axis_rx_tkeep(7 downto 1) => open,
m_axis_rx_tlast => m_axis_rx_tlast , m_axis_rx_tlast => m_axis_rx_tlast ,
m_axis_rx_tvalid => m_axis_rx_tvalid , m_axis_rx_tvalid => m_axis_rx_tvalid ,
m_axis_rx_tready => m_axis_rx_tready , m_axis_rx_tready => m_axis_rx_tready ,
...@@ -1536,7 +1535,7 @@ begin ...@@ -1536,7 +1535,7 @@ begin
-- 8. System(SYS) Interface -- -- 8. System(SYS) Interface --
------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------
sys_clk => sys_clk_c , sys_clk => sys_clk_c ,
sys_reset => sys_reset_c sys_rst_n => sys_reset_n_c
); );
-- --------------------------------------------------------------- -- ---------------------------------------------------------------
...@@ -1544,7 +1543,7 @@ begin ...@@ -1544,7 +1543,7 @@ begin
-- --------------------------------------------------------------- -- ---------------------------------------------------------------
-- workaround pcie core bug -- workaround pcie core bug
m_axis_rx_tkeep(7 downto 1) <= X"0" & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0); --m_axis_rx_tkeep(7 downto 1) <= X"0" & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0) & m_axis_rx_tkeep(0);
theTlpControl : theTlpControl :
tlpControl tlpControl
......
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