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Beam Positoning Monitor - Gateware
Commit 2ab2c9d7 authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_trigger: split module into 3 to allow more flexibility 

Now, instead of a single module wb_trigger,
we have 3 separate modules:

1) wb_trigger_iface responsible for the low-level
interface to board and FPGA

2) wb_trigger_mux responsible for multiplexing
multiple physical triggers (external trigger signals)
to multiple, independent, trigger interfaces (FPGA signals)

3) wb_trigger responsible for wrapping 1) and 2) together
and providing a resolution method for assigning physical
triggers to trigger interfaces (e.g., fanout resolution)
and a resolution method for collapsing trigger interfaces
to physical triggers (e.g, ORing trigger interface pulses)

This fixes #56 github issue
parent 8bb01d0e
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Showing with 34724 additions and 13415 deletions
hdl/modules/dbe_wishbone/Manifest.py
View file @ 2ab2c9d7
......@@ -2,6 +2,8 @@ files = [ "dbe_wishbone_pkg.vhd" ];
modules = { "local" : [
"wb_stream",
"wb_trigger_iface",
"wb_trigger_mux",
"wb_trigger",
"wb_fmc150",
"wb_fmc516",
......
hdl/modules/dbe_wishbone/wb_trigger/Manifest.py
View file @ 2ab2c9d7
files = [
"wb_trigger.vhd",
"xwb_trigger.vhd",
"wbgen/wb_slave_trigger.vhd",
"wbgen/wb_slave_trigger_regs_pkg.vhd"];
files = [
"trigger_pkg.vhd",
"trigger_resolver.vhd",
"wb_trigger.vhd",
"xwb_trigger.vhd"
];
hdl/modules/dbe_wishbone/wb_trigger/trigger_pkg.vhd 0 → 100644
View file @ 2ab2c9d7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.genram_pkg.all;
package trigger_pkg is
-- Constants
-- Types
subtype t_trig_pulse is std_logic;
type t_trig_pulse_array is array (natural range <>) of t_trig_pulse;
type t_trig_pulse_array2d is array (natural range <>, natural range <>) of t_trig_pulse;
type t_trig_channel is record
pulse : t_trig_pulse;
end record;
type t_trig_channel_array is array (natural range <>) of t_trig_channel;
type t_trig_channel_array2d is array (natural range <>, natural range <>) of t_trig_channel;
constant c_trig_channel_dummy : t_trig_channel := (pulse => '0');
component trigger_resolver
generic (
g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout";
g_in_resolver : string := "or"
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------
--- Trigger ports
-------------------------------
trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0)
);
end component;
end trigger_pkg;
hdl/modules/dbe_wishbone/wb_trigger/trigger_resolver.vhd 0 → 100644
View file @ 2ab2c9d7
------------------------------------------------------------------------
-- Title : Wishbone Trigger Interface
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_resolver.vhd
-- Author : Lucas Russo <lerwys@gmail.com>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-05-11
-- Last update:
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Top module for the Wishbone Trigger MUX interface
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-11 1.0 lerwys Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Reset Synch
use work.dbe_common_pkg.all;
-- Trigger types
use work.trigger_pkg.all;
entity trigger_resolver is
generic (
g_trig_num : natural := 8;
g_num_mux_interfaces : natural := 2;
g_out_resolver : string := "fanout";
g_in_resolver : string := "or"
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------
--- Trigger ports
-------------------------------
trig_resolved_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_resolved_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
trig_mux_out_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
trig_mux_in_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0)
);
end entity trigger_resolver;
architecture rtl of trigger_resolver is
signal trig_mux_out_int : t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_trig_num-1 downto 0);
signal trig_mux_in_int : t_trig_channel_array(g_trig_num-1 downto 0);
-- Trigger ordered by interfaces
subtype t_trig_interface_pulses is std_logic_vector(g_num_mux_interfaces-1 downto 0);
type t_trig_interface_pulses_array is array (natural range <>) of t_trig_interface_pulses;
signal trig_mux_in_interface_pulses : t_trig_interface_pulses_array(g_trig_num-1 downto 0);
-- From general-cores wb_crossbar module
-- If any of the bits are '1', the whole thing is '1'
-- This function makes the check explicitly have logarithmic depth.
function f_vector_OR(x : std_logic_vector)
return std_logic
is
constant len : integer := x'length;
constant mid : integer := len / 2;
alias y : std_logic_vector(len-1 downto 0) is x;
begin
if len = 1
then return y(0);
else return f_vector_OR(y(len-1 downto mid)) or
f_vector_OR(y(mid-1 downto 0));
end if;
end f_vector_OR;
begin -- architecture rtl
assert (g_out_resolver = "fanout") -- Output Resolver
report "[trigger_resolver] only g_out_resolver equal to ""fanout"" is supported!"
severity failure;
assert (g_in_resolver = "or") -- Input Resolver
report "[trigger_resolver] only g_in_resolver equal to ""or"" is supported!"
severity failure;
-- Generate Output
gen_output_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_output_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_output_resolver_fanout : if g_out_resolver = "fanout" generate
p_output : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trig_mux_out_int (i, j) <= c_trig_channel_dummy;
else
trig_mux_out_int (i, j) <= trig_resolved_in_i(j);
end if;
end if;
end process;
end generate;
end generate;
end generate;
trig_mux_out_o <= trig_mux_out_int;
-- Reorder input channels
gen_reorder_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_input_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
trig_mux_in_interface_pulses(j)(i) <= trig_mux_in_i(i, j).pulse;
end generate;
end generate;
-- Generate Inputs
gen_input_trigger_channels : for j in 0 to g_trig_num-1 generate
gen_input_resolver_or : if g_in_resolver = "or" generate
p_input : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
trig_mux_in_int(j) <= c_trig_channel_dummy;
else
trig_mux_in_int(j).pulse <= f_vector_OR(trig_mux_in_interface_pulses(j));
end if;
end if;
end process;
end generate;
end generate;
trig_resolved_out_o <= trig_mux_in_int;
end architecture rtl;
hdl/modules/dbe_wishbone/wb_trigger/wbgen/build_wb.sh deleted 100755 → 0
View file @ 8bb01d0e
#!/bin/bash
wbgen2 -V wb_slave_trigger.vhd -H record -p wb_slave_trigger_regs_pkg.vhd -K ../../../../sim/regs/wb_slave_trigger_regs.vh -s defines -C wb_slave_trigger_regs.h -f html -D doc/wb_slave_trigger_regs_wb.html wb_trigger.wb
hdl/modules/dbe_wishbone/wb_trigger/xwb_trigger.vhd 100755 → 100644
View file @ 2ab2c9d7
......@@ -7,6 +7,8 @@ library work;
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Trigger package
use work.trigger_pkg.all;
entity xwb_trigger is
generic
......@@ -14,10 +16,14 @@ entity xwb_trigger is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_sync_edge : string := "positive";
g_trig_num : natural range 1 to 24 := 8;
g_intern_num : natural range 1 to 24 := 8;
g_rcv_intern_num : natural range 1 to 24 := 2
);
g_trig_num : natural range 1 to 24 := 8; -- channels facing outside the FPGA. Limit defined by wb_trigger_regs.vhd
g_intern_num : natural range 1 to 24 := 8; -- channels facing inside the FPGA. Limit defined by wb_trigger_regs.vhd
g_rcv_intern_num : natural range 1 to 24 := 2; -- signals from inside the FPGA that can be used as input at a rcv mux.
-- Limit defined by wb_trigger_regs.vhd
g_num_mux_interfaces : natural := 2; -- Number of wb_trigger_mux modules
g_out_resolver : string := "fanout"; -- Resolver policy for output triggers
g_in_resolver : string := "or" -- Resolver policy for input triggers
);
port
(
rst_n_i : in std_logic;
......@@ -29,67 +35,134 @@ entity xwb_trigger is
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
wb_slv_trigger_iface_i : in t_wishbone_slave_in;
wb_slv_trigger_iface_o : out t_wishbone_slave_out;
wb_slv_trigger_mux_i : in t_wishbone_slave_in_array(g_num_mux_interfaces-1 downto 0);
wb_slv_trigger_mux_o : out t_wishbone_slave_out_array(g_num_mux_interfaces-1 downto 0);
-----------------------------
-- External ports
-----------------------------
trig_b : inout std_logic_vector(g_trig_num-1 downto 0);
trig_dir_o : out std_logic_vector(g_trig_num-1 downto 0);
trig_b : inout std_logic_vector(g_trig_num-1 downto 0);
trig_dir_o : out std_logic_vector(g_trig_num-1 downto 0);
-----------------------------
-- Internal ports
-----------------------------
trig_rcv_intern_i : in std_logic_vector(g_rcv_intern_num-1 downto 0);
trig_rcv_intern_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_rcv_intern_num-1 downto 0); -- signals from inside the FPGA that can be used as input at a rcv mux
trig_pulse_transm_i : in std_logic_vector(g_intern_num-1 downto 0);
trig_pulse_rcv_o : out std_logic_vector(g_intern_num-1 downto 0)
);
trig_pulse_transm_i : in t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
trig_pulse_rcv_o : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0)
);
end xwb_trigger;
architecture rtl of xwb_trigger is
-- Trigger 2d <-> 1d conversion
signal trig_rcv_intern_compat : t_trig_channel_array(g_num_mux_interfaces*g_rcv_intern_num-1 downto 0);
-- Trigger 2d <-> 1d conversion
signal trig_pulse_transm_compat : t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
signal trig_pulse_rcv_compat : t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
signal wb_slv_trigger_mux_adr_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_address_width-1 downto 0);
signal wb_slv_trigger_mux_dat_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width-1 downto 0);
signal wb_slv_trigger_mux_dat_out_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width-1 downto 0);
signal wb_slv_trigger_mux_sel_in_int : std_logic_vector(g_num_mux_interfaces*c_wishbone_data_width/8-1 downto 0);
signal wb_slv_trigger_mux_we_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_cyc_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_stb_in_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_ack_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_err_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_rty_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
signal wb_slv_trigger_mux_stall_out_int : std_logic_vector(g_num_mux_interfaces-1 downto 0);
begin
cmp_wb_trigger : wb_trigger
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_width_bus_size => g_width_bus_size,
g_rcv_len_bus_width => g_rcv_len_bus_width,
g_transm_len_bus_width => g_transm_len_bus_width,
g_sync_edge => g_sync_edge,
g_trig_num => g_trig_num,
g_intern_num => g_intern_num,
g_rcv_intern_num => g_rcv_intern_num,
g_counter_wid => g_counter_wid)
g_num_mux_interfaces => g_num_mux_interfaces,
g_out_resolver => g_out_resolver,
g_in_resolver => g_in_resolver
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
trig_dir_o => trig_dir_o,
trig_pulse_transm_i => trig_pulse_transm_i,
trig_pulse_rcv_o => trig_pulse_rcv_o,
trig_rcv_intern_i => trig_rcv_intern_i,
trig_b => trig_b);
wb_slv_o.int <= '0';
wb_trigger_iface_adr_i => wb_slv_trigger_iface_i.adr,
wb_trigger_iface_dat_i => wb_slv_trigger_iface_i.dat,
wb_trigger_iface_dat_o => wb_slv_trigger_iface_o.dat,
wb_trigger_iface_sel_i => wb_slv_trigger_iface_i.sel,
wb_trigger_iface_we_i => wb_slv_trigger_iface_i.we,
wb_trigger_iface_cyc_i => wb_slv_trigger_iface_i.cyc,
wb_trigger_iface_stb_i => wb_slv_trigger_iface_i.stb,
wb_trigger_iface_ack_o => wb_slv_trigger_iface_o.ack,
wb_trigger_iface_err_o => wb_slv_trigger_iface_o.err,
wb_trigger_iface_rty_o => wb_slv_trigger_iface_o.rty,
wb_trigger_iface_stall_o => wb_slv_trigger_iface_o.stall,
wb_trigger_mux_adr_i => wb_slv_trigger_mux_adr_in_int,
wb_trigger_mux_dat_i => wb_slv_trigger_mux_dat_in_int,
wb_trigger_mux_dat_o => wb_slv_trigger_mux_dat_out_int,
wb_trigger_mux_sel_i => wb_slv_trigger_mux_sel_in_int,
wb_trigger_mux_we_i => wb_slv_trigger_mux_we_in_int,
wb_trigger_mux_cyc_i => wb_slv_trigger_mux_cyc_in_int,
wb_trigger_mux_stb_i => wb_slv_trigger_mux_stb_in_int,
wb_trigger_mux_ack_o => wb_slv_trigger_mux_ack_out_int,
wb_trigger_mux_err_o => wb_slv_trigger_mux_err_out_int,
wb_trigger_mux_rty_o => wb_slv_trigger_mux_rty_out_int,
wb_trigger_mux_stall_o => wb_slv_trigger_mux_stall_out_int,
trig_b => trig_b,
trig_dir_o => trig_dir_o,
trig_rcv_intern_i => trig_rcv_intern_compat,
trig_pulse_transm_i => trig_pulse_transm_compat,
trig_pulse_rcv_o => trig_pulse_rcv_compat
);
gen_wb_slv_trigger_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
wb_slv_trigger_mux_adr_in_int((i+1)*c_wishbone_address_width-1 downto i*c_wishbone_address_width) <= wb_slv_trigger_mux_i(i).adr;
wb_slv_trigger_mux_sel_in_int((i+1)*c_wishbone_data_width/8-1 downto i*c_wishbone_data_width/8) <= wb_slv_trigger_mux_i(i).sel;
wb_slv_trigger_mux_dat_in_int((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width) <= wb_slv_trigger_mux_i(i).dat;
wb_slv_trigger_mux_cyc_in_int(i) <= wb_slv_trigger_mux_i(i).cyc;
wb_slv_trigger_mux_stb_in_int(i) <= wb_slv_trigger_mux_i(i).stb;
wb_slv_trigger_mux_we_in_int(i) <= wb_slv_trigger_mux_i(i).we;
wb_slv_trigger_mux_o(i).dat <= wb_slv_trigger_mux_dat_out_int((i+1)*c_wishbone_data_width-1 downto i*c_wishbone_data_width);
wb_slv_trigger_mux_o(i).ack <= wb_slv_trigger_mux_ack_out_int(i);
wb_slv_trigger_mux_o(i).stall <= wb_slv_trigger_mux_stall_out_int(i);
wb_slv_trigger_mux_o(i).err <= wb_slv_trigger_mux_err_out_int(i);
wb_slv_trigger_mux_o(i).rty <= wb_slv_trigger_mux_rty_out_int(i);
end generate;
-- Convert 1d <-> 2d vectors
gen_compat_interfaces : for i in 0 to g_num_mux_interfaces-1 generate
gen_rcv_intern_compat_trigger_channels : for j in 0 to g_rcv_intern_num-1 generate
trig_rcv_intern_compat(i*g_rcv_intern_num + j) <= trig_rcv_intern_i(i, j);
end generate;
gen_compat_trigger_channels : for j in 0 to g_intern_num-1 generate
trig_pulse_transm_compat(i*g_intern_num + j) <= trig_pulse_transm_i(i, j);
trig_pulse_rcv_o(i, j) <= trig_pulse_rcv_compat(i*g_intern_num + j);
end generate;
end generate;
end rtl;
hdl/modules/dbe_wishbone/wb_trigger_iface/Manifest.py 0 → 100644
View file @ 2ab2c9d7
files = [
"wb_trigger_iface.vhd",
"xwb_trigger_iface.vhd",
"wbgen/wb_trigger_iface_regs.vhd",
"wbgen/wb_trigger_iface_regs_pkg.vhd"];
hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd 0 → 100644
View file @ 2ab2c9d7
This diff is collapsed.
hdl/modules/dbe_wishbone/wb_trigger_iface/wbgen/build_wb.sh 0 → 100755
View file @ 2ab2c9d7
#!/bin/bash
wbgen2 -V wb_trigger_iface_regs.vhd -H record -p wb_trigger_iface_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_iface_regs.vh -s defines -C wb_trigger_iface_regs.h -f html -D doc/wb_trigger_iface_regs_wb.html wb_trigger_iface.wb
hdl/modules/dbe_wishbone/wb_trigger_iface/xwb_trigger_iface.vhd 0 → 100644
View file @ 2ab2c9d7
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Trigger definitions
use work.trigger_pkg.all;
entity xwb_trigger_iface is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_sync_edge : string := "positive";
g_trig_num : natural range 1 to 24 := 8
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
trig_b : inout std_logic_vector(g_trig_num-1 downto 0);
trig_dir_o : out std_logic_vector(g_trig_num-1 downto 0);
-----------------------------
-- Internal ports
-----------------------------
trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_in_i : in t_trig_channel_array(g_trig_num-1 downto 0)
);
end xwb_trigger_iface;
architecture rtl of xwb_trigger_iface is
begin
cmp_wb_trigger_iface : wb_trigger_iface
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_sync_edge => g_sync_edge,
g_trig_num => g_trig_num
)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
trig_b => trig_b,
trig_dir_o => trig_dir_o,
trig_out_o => trig_out_o,
trig_in_i => trig_in_i
);
end rtl;
hdl/modules/dbe_wishbone/wb_trigger_mux/Manifest.py 0 → 100644
View file @ 2ab2c9d7
files = [
"wb_trigger_mux.vhd",
"xwb_trigger_mux.vhd",
"wbgen/wb_trigger_mux_regs.vhd",
"wbgen/wb_trigger_mux_regs_pkg.vhd"];
hdl/modules/dbe_wishbone/wb_trigger_mux/wb_trigger_mux.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_trigger_mux/wbgen/build_wb.sh 0 → 100755
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#!/bin/bash
wbgen2 -V wb_trigger_mux_regs.vhd -H record -p wb_trigger_mux_regs_pkg.vhd -K ../../../../sim/regs/wb_trigger_mux_regs.vh -s defines -C wb_trigger_mux_regs.h -f html -D doc/wb_trigger_mux_regs_wb.html wb_trigger_mux.wb
hdl/modules/dbe_wishbone/wb_trigger_mux/xwb_trigger_mux.vhd 0 → 100644
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Custom Wishbone Modules
use work.dbe_wishbone_pkg.all;
-- Trigger definitions
use work.trigger_pkg.all;
entity xwb_trigger is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_trig_num : natural range 1 to 24 := 8;
g_intern_num : natural range 1 to 24 := 8;
g_rcv_intern_num : natural range 1 to 24 := 2
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
fs_clk_i : in std_logic;
fs_rst_n_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
trig_in_i : in t_trig_channel_array(g_trig_num-1 downto 0);
-----------------------------
-- Internal ports
-----------------------------
trig_rcv_intern_i : in t_trig_channel_array(g_rcv_intern_num-1 downto 0);
trig_pulse_transm_i : in t_trig_channel_array(g_intern_num-1 downto 0);
trig_pulse_rcv_o : out t_trig_channel_array(g_intern_num-1 downto 0)
);
end xwb_trigger;
architecture rtl of xwb_trigger is
begin
cmp_wb_trigger : wb_trigger
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_trig_num => g_trig_num,
g_intern_num => g_intern_num,
g_rcv_intern_num => g_rcv_intern_num)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_err_o => wb_slv_o.err,
wb_rty_o => wb_slv_o.rty,
wb_stall_o => wb_slv_o.stall,
trig_out_o => trig_out_o,
trig_in_i => trig_in_i,
trig_rcv_intern_i => trig_rcv_intern_i,
trig_pulse_transm_i => trig_pulse_transm_i,
trig_pulse_rcv_o => trig_pulse_rcv_o
);
end rtl;
hdl/sim/regs/wb_slave_trigger_regs.vh deleted 100644 → 0
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hdl/sim/regs/wb_trigger_iface_regs.vh 0 → 100644
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hdl/sim/regs/wb_trigger_mux_regs.vh 0 → 100644
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