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Commit 2b8105dd authored by Lucas Russo's avatar Lucas Russo
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wb_fmc516/wbgen/*: (1/3) add regular delay control register

parent 93b7d8c8
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Showing with 580 additions and 72 deletions
hdl/modules/custom_wishbone/wb_fmc516/wbgen/doc/fmc516_regs_wb.html
View file @ 2b8105dd
......@@ -1326,7 +1326,41 @@ fmc516_ch0_dly_ctl_fe_dly_o[1:0]
</td>
<td class="td_pblock_right">
fmc516_ch0_dly_ctl_reserved_fe_dly_o[29:0]
fmc516_ch0_dly_ctl_reserved_fe_dly_o[5:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch0_dly_ctl_rg_dly_o[1:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch0_dly_ctl_reserved_rg_dly_o[21:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -1734,7 +1768,41 @@ fmc516_ch1_dly_ctl_fe_dly_o[1:0]
</td>
<td class="td_pblock_right">
fmc516_ch1_dly_ctl_reserved_fe_dly_o[29:0]
fmc516_ch1_dly_ctl_reserved_fe_dly_o[5:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch1_dly_ctl_rg_dly_o[1:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch1_dly_ctl_reserved_rg_dly_o[21:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2142,7 +2210,41 @@ fmc516_ch2_dly_ctl_fe_dly_o[1:0]
</td>
<td class="td_pblock_right">
fmc516_ch2_dly_ctl_reserved_fe_dly_o[29:0]
fmc516_ch2_dly_ctl_reserved_fe_dly_o[5:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch2_dly_ctl_rg_dly_o[1:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch2_dly_ctl_reserved_rg_dly_o[21:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -2550,7 +2652,41 @@ fmc516_ch3_dly_ctl_fe_dly_o[1:0]
</td>
<td class="td_pblock_right">
fmc516_ch3_dly_ctl_reserved_fe_dly_o[29:0]
fmc516_ch3_dly_ctl_reserved_fe_dly_o[5:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch3_dly_ctl_rg_dly_o[1:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc516_ch3_dly_ctl_reserved_rg_dly_o[21:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -4552,7 +4688,7 @@ CH0_DLY_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[29:22]
RESERVED_RG_DLY[21:14]
</td>
<td >
......@@ -4606,7 +4742,7 @@ RESERVED_FE_DLY[29:22]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[21:14]
RESERVED_RG_DLY[13:6]
</td>
<td >
......@@ -4659,11 +4795,11 @@ RESERVED_FE_DLY[21:14]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[13:6]
<td style="border: solid 1px black;" colspan=6 class="td_field">
RESERVED_RG_DLY[5:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=2 class="td_field">
RG_DLY[1:0]
</td>
<td >
......@@ -4748,6 +4884,14 @@ FE_DLY
RESERVED_FE_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
<li><b>
RG_DLY
</b>[<i>read/write</i>]: Regular data delay
<br>write 3: delay data by two.<br> write 1: delay data by one.<br> write 0: no effect
<li><b>
RESERVED_RG_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
</ul>
<a name="CH1_STA"></a>
<h3><a name="sect_3_9">3.9. Channel 1 status register</a></h3>
......@@ -5370,7 +5514,7 @@ CH1_DLY_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[29:22]
RESERVED_RG_DLY[21:14]
</td>
<td >
......@@ -5424,7 +5568,7 @@ RESERVED_FE_DLY[29:22]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[21:14]
RESERVED_RG_DLY[13:6]
</td>
<td >
......@@ -5477,11 +5621,11 @@ RESERVED_FE_DLY[21:14]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[13:6]
<td style="border: solid 1px black;" colspan=6 class="td_field">
RESERVED_RG_DLY[5:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=2 class="td_field">
RG_DLY[1:0]
</td>
<td >
......@@ -5566,6 +5710,14 @@ FE_DLY
RESERVED_FE_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
<li><b>
RG_DLY
</b>[<i>read/write</i>]: Regular data delay
<br>write 3: delay data by two.<br> write 1: delay data by one.<br> write 0: no effect
<li><b>
RESERVED_RG_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
</ul>
<a name="CH2_STA"></a>
<h3><a name="sect_3_12">3.12. Channel 2 status register</a></h3>
......@@ -6188,7 +6340,7 @@ CH2_DLY_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[29:22]
RESERVED_RG_DLY[21:14]
</td>
<td >
......@@ -6242,7 +6394,7 @@ RESERVED_FE_DLY[29:22]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[21:14]
RESERVED_RG_DLY[13:6]
</td>
<td >
......@@ -6295,11 +6447,11 @@ RESERVED_FE_DLY[21:14]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[13:6]
<td style="border: solid 1px black;" colspan=6 class="td_field">
RESERVED_RG_DLY[5:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=2 class="td_field">
RG_DLY[1:0]
</td>
<td >
......@@ -6384,6 +6536,14 @@ FE_DLY
RESERVED_FE_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
<li><b>
RG_DLY
</b>[<i>read/write</i>]: Regular data delay
<br>write 3: delay data by two.<br> write 1: delay data by one.<br> write 0: no effect
<li><b>
RESERVED_RG_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
</ul>
<a name="CH3_STA"></a>
<h3><a name="sect_3_15">3.15. Channel 3 status register</a></h3>
......@@ -7006,7 +7166,7 @@ CH3_DLY_CTL
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[29:22]
RESERVED_RG_DLY[21:14]
</td>
<td >
......@@ -7060,7 +7220,7 @@ RESERVED_FE_DLY[29:22]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[21:14]
RESERVED_RG_DLY[13:6]
</td>
<td >
......@@ -7113,11 +7273,11 @@ RESERVED_FE_DLY[21:14]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED_FE_DLY[13:6]
<td style="border: solid 1px black;" colspan=6 class="td_field">
RESERVED_RG_DLY[5:0]
</td>
<td >
<td style="border: solid 1px black;" colspan=2 class="td_field">
RG_DLY[1:0]
</td>
<td >
......@@ -7202,6 +7362,14 @@ FE_DLY
RESERVED_FE_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
<li><b>
RG_DLY
</b>[<i>read/write</i>]: Regular data delay
<br>write 3: delay data by two.<br> write 1: delay data by one.<br> write 0: no effect
<li><b>
RESERVED_RG_DLY
</b>[<i>read/write</i>]: Reserved
<br>Ignore on write, read as 0's
</ul>
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/fmc516_regs.h
View file @ 2b8105dd
......@@ -3,7 +3,7 @@
* File : fmc516_regs.h
* Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
* Created : Mon Mar 18 15:23:00 2013
* Created : Thu Mar 28 10:43:19 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -213,10 +213,22 @@
#define FMC516_CH0_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH0_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH0_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH0_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 0 delay control register */
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 1 status register */
......@@ -291,10 +303,22 @@
#define FMC516_CH1_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH1_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH1_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH1_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 1 delay control register */
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 2 status register */
......@@ -369,10 +393,22 @@
#define FMC516_CH2_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH2_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH2_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH2_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 2 delay control register */
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
/* definitions for register: Channel 3 status register */
......@@ -447,10 +483,22 @@
#define FMC516_CH3_DLY_CTL_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_MASK WBGEN2_GEN_MASK(2, 6)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_SHIFT 2
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 30)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_W(value) WBGEN2_GEN_WRITE(value, 2, 6)
#define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_R(reg) WBGEN2_GEN_READ(reg, 2, 6)
/* definitions for field: Regular data delay in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RG_DLY_MASK WBGEN2_GEN_MASK(8, 2)
#define FMC516_CH3_DLY_CTL_RG_DLY_SHIFT 8
#define FMC516_CH3_DLY_CTL_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 8, 2)
#define FMC516_CH3_DLY_CTL_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 8, 2)
/* definitions for field: Reserved in reg: Channel 3 delay control register */
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_MASK WBGEN2_GEN_MASK(10, 22)
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_SHIFT 10
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_W(value) WBGEN2_GEN_WRITE(value, 10, 22)
#define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_R(reg) WBGEN2_GEN_READ(reg, 10, 22)
PACKED struct FMC516_WB {
/* [0x0]: REG Status register */
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.wb
View file @ 2b8105dd
......@@ -492,7 +492,31 @@ peripheral {
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Regular data delay";
description = "write 3: delay data by two.\
write 1: delay data by one.\
write 0: no effect";
prefix = "rg_dly";
type = SLV;
clock = "fs_clk_i";
align = 8;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_rg_dly";
type = SLV;
size = 22;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -679,7 +703,31 @@ peripheral {
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Regular data delay";
description = "write 3: delay data by two.\
write 1: delay data by one.\
write 0: no effect";
prefix = "rg_dly";
type = SLV;
clock = "fs_clk_i";
align = 8;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_rg_dly";
type = SLV;
size = 22;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -865,7 +913,31 @@ peripheral {
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Regular data delay";
description = "write 3: delay data by two.\
write 1: delay data by one.\
write 0: no effect";
prefix = "rg_dly";
type = SLV;
clock = "fs_clk_i";
align = 8;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_rg_dly";
type = SLV;
size = 22;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......@@ -1051,7 +1123,31 @@ peripheral {
description = "Ignore on write, read as 0's";
prefix = "reserved_fe_dly";
type = SLV;
size = 30;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Regular data delay";
description = "write 3: delay data by two.\
write 1: delay data by one.\
write 0: no effect";
prefix = "rg_dly";
type = SLV;
clock = "fs_clk_i";
align = 8;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on write, read as 0's";
prefix = "reserved_rg_dly";
type = SLV;
size = 22;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
......
hdl/modules/custom_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd
View file @ 2b8105dd
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc516_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created : Mon Mar 18 15:23:00 2013
-- Created : Thu Mar 28 10:43:19 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
......@@ -122,7 +122,9 @@ package fmc516_wbgen2_pkg is
ch0_ctl_dec_data_chain_dly_o : std_logic;
ch0_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch0_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch0_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch0_dly_ctl_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch0_dly_ctl_rg_dly_o : std_logic_vector(1 downto 0);
ch0_dly_ctl_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch1_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch1_ctl_clk_chain_dly_load_o : std_logic;
ch1_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -134,7 +136,9 @@ package fmc516_wbgen2_pkg is
ch1_ctl_dec_data_chain_dly_o : std_logic;
ch1_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch1_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch1_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch1_dly_ctl_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch1_dly_ctl_rg_dly_o : std_logic_vector(1 downto 0);
ch1_dly_ctl_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch2_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch2_ctl_clk_chain_dly_load_o : std_logic;
ch2_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -146,7 +150,9 @@ package fmc516_wbgen2_pkg is
ch2_ctl_dec_data_chain_dly_o : std_logic;
ch2_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch2_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch2_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch2_dly_ctl_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch2_dly_ctl_rg_dly_o : std_logic_vector(1 downto 0);
ch2_dly_ctl_reserved_rg_dly_o : std_logic_vector(21 downto 0);
ch3_ctl_clk_chain_dly_o : std_logic_vector(4 downto 0);
ch3_ctl_clk_chain_dly_load_o : std_logic;
ch3_ctl_data_chain_dly_o : std_logic_vector(4 downto 0);
......@@ -158,7 +164,9 @@ package fmc516_wbgen2_pkg is
ch3_ctl_dec_data_chain_dly_o : std_logic;
ch3_ctl_reserved_data_incdec_dly_o : std_logic_vector(5 downto 0);
ch3_dly_ctl_fe_dly_o : std_logic_vector(1 downto 0);
ch3_dly_ctl_reserved_fe_dly_o : std_logic_vector(29 downto 0);
ch3_dly_ctl_reserved_fe_dly_o : std_logic_vector(5 downto 0);
ch3_dly_ctl_rg_dly_o : std_logic_vector(1 downto 0);
ch3_dly_ctl_reserved_rg_dly_o : std_logic_vector(21 downto 0);
end record;
constant c_fmc516_out_registers_init_value: t_fmc516_out_registers := (
......@@ -187,6 +195,8 @@ package fmc516_wbgen2_pkg is
ch0_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch0_dly_ctl_fe_dly_o => (others => '0'),
ch0_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch0_dly_ctl_rg_dly_o => (others => '0'),
ch0_dly_ctl_reserved_rg_dly_o => (others => '0'),
ch1_ctl_clk_chain_dly_o => (others => '0'),
ch1_ctl_clk_chain_dly_load_o => '0',
ch1_ctl_data_chain_dly_o => (others => '0'),
......@@ -199,6 +209,8 @@ package fmc516_wbgen2_pkg is
ch1_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch1_dly_ctl_fe_dly_o => (others => '0'),
ch1_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch1_dly_ctl_rg_dly_o => (others => '0'),
ch1_dly_ctl_reserved_rg_dly_o => (others => '0'),
ch2_ctl_clk_chain_dly_o => (others => '0'),
ch2_ctl_clk_chain_dly_load_o => '0',
ch2_ctl_data_chain_dly_o => (others => '0'),
......@@ -211,6 +223,8 @@ package fmc516_wbgen2_pkg is
ch2_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch2_dly_ctl_fe_dly_o => (others => '0'),
ch2_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch2_dly_ctl_rg_dly_o => (others => '0'),
ch2_dly_ctl_reserved_rg_dly_o => (others => '0'),
ch3_ctl_clk_chain_dly_o => (others => '0'),
ch3_ctl_clk_chain_dly_load_o => '0',
ch3_ctl_data_chain_dly_o => (others => '0'),
......@@ -222,7 +236,9 @@ package fmc516_wbgen2_pkg is
ch3_ctl_dec_data_chain_dly_o => '0',
ch3_ctl_reserved_data_incdec_dly_o => (others => '0'),
ch3_dly_ctl_fe_dly_o => (others => '0'),
ch3_dly_ctl_reserved_fe_dly_o => (others => '0')
ch3_dly_ctl_reserved_fe_dly_o => (others => '0'),
ch3_dly_ctl_rg_dly_o => (others => '0'),
ch3_dly_ctl_reserved_rg_dly_o => (others => '0')
);
function "or" (left, right: t_fmc516_in_registers) return t_fmc516_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
hdl/sim/regs/wb_fmc516_regs.vh
View file @ 2b8105dd
......@@ -81,7 +81,11 @@
`define FMC516_CH0_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH0_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define FMC516_CH0_DLY_CTL_RESERVED_FE_DLY 32'h000000fc
`define FMC516_CH0_DLY_CTL_RG_DLY_OFFSET 8
`define FMC516_CH0_DLY_CTL_RG_DLY 32'h00000300
`define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY_OFFSET 10
`define FMC516_CH0_DLY_CTL_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_FMC516_CH1_STA 7'h20
`define FMC516_CH1_STA_VAL_OFFSET 0
`define FMC516_CH1_STA_VAL 32'h0000ffff
......@@ -112,7 +116,11 @@
`define FMC516_CH1_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH1_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define FMC516_CH1_DLY_CTL_RESERVED_FE_DLY 32'h000000fc
`define FMC516_CH1_DLY_CTL_RG_DLY_OFFSET 8
`define FMC516_CH1_DLY_CTL_RG_DLY 32'h00000300
`define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY_OFFSET 10
`define FMC516_CH1_DLY_CTL_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_FMC516_CH2_STA 7'h2c
`define FMC516_CH2_STA_VAL_OFFSET 0
`define FMC516_CH2_STA_VAL 32'h0000ffff
......@@ -143,7 +151,11 @@
`define FMC516_CH2_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH2_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define FMC516_CH2_DLY_CTL_RESERVED_FE_DLY 32'h000000fc
`define FMC516_CH2_DLY_CTL_RG_DLY_OFFSET 8
`define FMC516_CH2_DLY_CTL_RG_DLY 32'h00000300
`define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY_OFFSET 10
`define FMC516_CH2_DLY_CTL_RESERVED_RG_DLY 32'hfffffc00
`define ADDR_FMC516_CH3_STA 7'h38
`define FMC516_CH3_STA_VAL_OFFSET 0
`define FMC516_CH3_STA_VAL 32'h0000ffff
......@@ -174,4 +186,8 @@
`define FMC516_CH3_DLY_CTL_FE_DLY_OFFSET 0
`define FMC516_CH3_DLY_CTL_FE_DLY 32'h00000003
`define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY_OFFSET 2
`define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY 32'hfffffffc
`define FMC516_CH3_DLY_CTL_RESERVED_FE_DLY 32'h000000fc
`define FMC516_CH3_DLY_CTL_RG_DLY_OFFSET 8
`define FMC516_CH3_DLY_CTL_RG_DLY 32'h00000300
`define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY_OFFSET 10
`define FMC516_CH3_DLY_CTL_RESERVED_RG_DLY 32'hfffffc00
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