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Beam Positoning Monitor - Gateware
Commit 38289cb3 authored by Lucas Russo's avatar Lucas Russo
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syn/afc_v1/*: rename syn design files to "dbe_bpm"

parent fea679ea
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Showing with 17 additions and 17 deletions
hdl/syn/afc_v1/dbe_bpm_dsp_fmc130m_4ch/Manifest.py → hdl/syn/afc_v1/dbe_bpm/Manifest.py
View file @ 38289cb3
......@@ -4,9 +4,9 @@ action = "synthesis"
syn_device = "xc7a200t"
syn_grade = "-1"
syn_package = "ffg1156"
syn_top = "dbe_bpm_dsp"
syn_project = "dbe_bpm_dsp.xise"
syn_top = "dbe_bpm"
syn_project = "dbe_bpm.xise"
syn_tool = "ise"
syn_ise_version = "14.6"
modules = { "local" : [ "../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch" ] };
modules = { "local" : [ "../../../top/afc_v1/dbe_bpm" ] };
hdl/syn/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xise → hdl/syn/afc_v1/dbe_bpm/dbe_bpm.xise
View file @ 38289cb3
......@@ -134,8 +134,8 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dbe_bpm_dsp" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dbe_bpm_dsp" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|dbe_bpm" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dbe_bpm" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -154,7 +154,7 @@
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Selected UCF File" xil_pn:value="/home/lerwys/Repos/bpm-sw/hdl/top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Selected UCF File" xil_pn:value="/home/lerwys/Repos/bpm-sw/hdl/top/afc_v1/dbe_bpm/dbe_bpm.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -193,7 +193,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="dbe_bpm_dsp" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="dbe_bpm" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -207,10 +207,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="dbe_bpm_dsp_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="dbe_bpm_dsp_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="dbe_bpm_dsp_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="dbe_bpm_dsp_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="dbe_bpm_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="dbe_bpm_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="dbe_bpm_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="dbe_bpm_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -326,7 +326,7 @@
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="dbe_bpm_dsp" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="dbe_bpm" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -343,7 +343,7 @@
<libraries/>
<files>
<file xil_pn:name="../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../top/afc_v1/dbe_bpm/dbe_bpm.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/artix7/cc_cmplr_v3_0_e58a4eb9f6488d2d.ngc" xil_pn:type="FILE_NGC">
......@@ -406,7 +406,7 @@
<file xil_pn:name="../../../platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="../../../top/afc_v1/dbe_bpm/position_calc_core.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/artix7/cntr_11_0_eb46eda57512a5a4.ngc" xil_pn:type="FILE_NGC">
......@@ -508,7 +508,7 @@
<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/clk_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../top/afc_v1/dbe_bpm/clk_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
......@@ -658,7 +658,7 @@
<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/sys_pll.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../top/afc_v1/dbe_bpm/sys_pll.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../../ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_axi_basic_top.v" xil_pn:type="FILE_VERILOG">
......@@ -1660,7 +1660,7 @@
<file xil_pn:name="../../../ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_axi_basic_tx.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="439"/>
</file>
<file xil_pn:name="../../../top/afc_v1/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../top/afc_v1/dbe_bpm/dbe_bpm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="440"/>
</file>
<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" xil_pn:type="FILE_VHDL">
......
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