Fix PCIe lane order for AFCv3. Enable higher quality DDR input clock

3babcdcb · Adrian Byszuk · 34fd541a · 3babcdcb · 3babcdcb
Commit 3babcdcb authored Oct 03, 2015 by Adrian Byszuk
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afcv3.xdc hdl/syn/pcie/afcv3.xdc +18 -0

top_afcv3.vhd hdl/top/pcie/top_afcv3.vhd +3 -0

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--- a/hdl/syn/pcie/afcv3.xdc
+++ b/hdl/syn/pcie/afcv3.xdc
@@ -20,6 +20,24 @@ set_property IN_TERM UNTUNED_SPLIT_50 [get_ports ddr_sys_clk_n]
 #place DDR input PLL close input pins and DDR logic
 set_property LOC PLLE2_ADV_X1Y1 [get_cells plle2_adv_inst]

+#XDC supplied by PCIe IP core generates GTP connection in reverse order, we have to swap it.
+#Simply providing correct connections will generate errors "Cannot set LOC ... because the bel is occupied by ..."
+#So, firstly set PCIe lanes to temporary locations
+set_property LOC GTPE2_CHANNEL_X0Y0 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y1 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+# ..., and then the correct ones:
+# PCIe Lane 0
+set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+# PCIe Lane 1
+set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+# PCIe Lane 2
+set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+# PCIe Lane 3
+set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells -hier -filter {name=~ */pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}]
+
+
 ### Timing constraints
 create_clock -name pci_sys_clk -period 10 [get_ports pci_sys_clk_p]


--- a/hdl/top/pcie/top_afcv3.vhd
+++ b/hdl/top/pcie/top_afcv3.vhd
@@ -213,6 +213,9 @@ begin
    );

  ddr_inclk_buf : IBUFGDS
+    generic map(
+      IBUF_LOW_PWR => false
+    )
    port map
     (o  => pll_clkin,
      i  => ddr_sys_clk_p,