Added Manifest and constraints file for receiver synthesis

3eea5415 · Vitor Finotti · dfdc3e8a · 3eea5415 · 3eea5415
Commit 3eea5415 authored Dec 18, 2015 by Vitor Finotti
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Manifest.py hdl/syn/afc_v3/vivado/test_trigger/rcv/Manifest.py +14 -0

test_trigger_rcv.xdc hdl/syn/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc +62 -0

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--- a/hdl/syn/afc_v3/vivado/test_trigger/rcv/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/test_trigger/rcv/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7a200t"
+syn_grade = "-1"
+syn_package = "ffg1156"
+syn_top = "test_trigger_rcv"
+syn_project = "test_trigger_rcv"
+syn_tool = "vivado"
+
+machine_pkg = "uvx_130M"
+
+modules = { "local" : [ "../../../../../top/afc_v3/vivado/test_trigger/rcv/" ] };
+
--- a/hdl/syn/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc
+++ b/hdl/syn/afc_v3/vivado/test_trigger/rcv/test_trigger_rcv.xdc
+create_clock -period 8.000 -name sys_clk_p_i [get_ports sys_clk_p_i]
+
+
+#// FPGA_CLK1_P
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p_i]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_p_i]
+#// FPGA_CLK1_N
+set_property PACKAGE_PIN AL7 [get_ports sys_clk_n_i]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n_i]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports sys_clk_n_i]
+
+
+#Signal
+set_property PACKAGE_PIN AM9 [get_ports {trigger_i[0]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[0]}]
+
+set_property PACKAGE_PIN AP11 [get_ports {trigger_i[1]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[1]}]
+
+set_property PACKAGE_PIN AP10 [get_ports {trigger_i[2]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[2]}]
+
+set_property PACKAGE_PIN AM11 [get_ports {trigger_i[3]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[3]}]
+
+set_property PACKAGE_PIN AN8 [get_ports {trigger_i[4]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[4]}]
+
+set_property PACKAGE_PIN AP8 [get_ports {trigger_i[5]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[5]}]
+
+set_property PACKAGE_PIN AL8 [get_ports {trigger_i[6]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[6]}]
+
+set_property PACKAGE_PIN AL9 [get_ports {trigger_i[7]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {trigger_i[7]}]
+
+#Direction
+
+# set_property PACKAGE_PIN AJ10 [get_ports {direction_o[0]}]
+# set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[0]}]
+
+set_property PACKAGE_PIN AK11 [get_ports {direction_o[1]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[1]}]
+
+set_property PACKAGE_PIN AJ11 [get_ports {direction_o[2]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[2]}]
+
+set_property PACKAGE_PIN AL10 [get_ports {direction_o[3]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[3]}]
+
+set_property PACKAGE_PIN AM10 [get_ports {direction_o[4]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[4]}]
+
+set_property PACKAGE_PIN AN11 [get_ports {direction_o[5]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[5]}]
+
+set_property PACKAGE_PIN AN9 [get_ports {direction_o[6]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[6]}]
+
+set_property PACKAGE_PIN AP9 [get_ports {direction_o[7]}]
+set_property IOSTANDARD LVCMOS15  [get_ports {direction_o[7]}]