Skip to content

B
Beam Positoning Monitor - Gateware
Commit 3f0f971f authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

modules/*/wb_fmcpico1m_4ch/*: renamed wbgen files/scripts 

This is just for consistency. No actual
changes made.
parent b2189414
Hide whitespace changes
Inline Side-by-side
Showing with 46 additions and 15 deletions
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/build_wb.sh
View file @ 3f0f971f
#!/bin/bash
wbgen2 -V fmc_pico1m_4ch_regs.vhd -H record -p fmc_pico1m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmcpico1m_4ch_regs.vh -s defines -C fmcpico1m_4ch_regs.h -f html -D doc/fmcpico1m_4ch_regs_wb.html fmc_pico1m_4ch_regs.wb
wbgen2 -V wb_fmcpico1m_4ch_regs.vhd -H record -p wb_fmcpico1m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmcpico1m_4ch_regs.vh -s defines -C wb_fmcpico1m_4ch_regs.h -f html -D doc/fmcpico1m_4ch_regs_wb.html wb_fmcpico1m_4ch_regs.wb
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmcpico1m_4ch_regs.h → hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.h
View file @ 3f0f971f
/*
Register definitions for slave core: Control and status registers for FMC PICO 1M 4CH
* File : fmcpico1m_4ch_regs.h
* Author : auto-generated by wbgen2 from fmc_pico1m_4ch_regs.wb
* Created : Tue Dec 8 15:27:17 2015
* File : wb_fmcpico1m_4ch_regs.h
* Author : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
* Created : Wed Mar 15 18:44:22 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_pico1m_4ch_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FMC_PICO1M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_FMC_PICO1M_4CH_REGS_WB
#ifndef __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB
#include <inttypes.h>
......
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmc_pico1m_4ch_regs.vhd → hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.vhd
View file @ 3f0f971f
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Control and status registers for FMC PICO 1M 4CH
---------------------------------------------------------------------------------------
-- File : fmc_pico1m_4ch_regs.vhd
-- Author : auto-generated by wbgen2 from fmc_pico1m_4ch_regs.wb
-- Created : Tue Dec 8 15:27:17 2015
-- File : wb_fmcpico1m_4ch_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
-- Created : Wed Mar 15 18:44:22 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_pico1m_4ch_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......
hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/fmc_pico1m_4ch_regs_pkg.vhd → hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs_pkg.vhd
View file @ 3f0f971f
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Control and status registers for FMC PICO 1M 4CH
---------------------------------------------------------------------------------------
-- File : fmc_pico1m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_pico1m_4ch_regs.wb
-- Created : Tue Dec 8 15:27:17 2015
-- File : wb_fmcpico1m_4ch_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
-- Created : Wed Mar 15 18:44:22 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_pico1m_4ch_regs.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......
hdl/sim/regs/wb_fmcpico1m_4ch_regs.vh 0 → 100644
View file @ 3f0f971f
`define ADDR_WB_FMC_PICO1M_4CH_CSR_FMC_STATUS 5'h0
`define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PRSNT_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PRSNT 32'h00000001
`define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PG_M2C_OFFSET 1
`define WB_FMC_PICO1M_4CH_CSR_FMC_STATUS_PG_M2C 32'h00000002
`define ADDR_WB_FMC_PICO1M_4CH_CSR_FMC_CTL 5'h4
`define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED1_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED1 32'h00000001
`define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED2_OFFSET 1
`define WB_FMC_PICO1M_4CH_CSR_FMC_CTL_LED2 32'h00000002
`define ADDR_WB_FMC_PICO1M_4CH_CSR_RNG_CTL 5'h8
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R0_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R0 32'h00000001
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R1_OFFSET 8
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R1 32'h00000100
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R2_OFFSET 16
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R2 32'h00010000
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R3_OFFSET 24
`define WB_FMC_PICO1M_4CH_CSR_RNG_CTL_R3 32'h01000000
`define ADDR_WB_FMC_PICO1M_4CH_CSR_DATA0 5'hc
`define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_DATA0_VAL 32'hffffffff
`define ADDR_WB_FMC_PICO1M_4CH_CSR_DATA1 5'h10
`define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_DATA1_VAL 32'hffffffff
`define ADDR_WB_FMC_PICO1M_4CH_CSR_DATA2 5'h14
`define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_DATA2_VAL 32'hffffffff
`define ADDR_WB_FMC_PICO1M_4CH_CSR_DATA3 5'h18
`define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL_OFFSET 0
`define WB_FMC_PICO1M_4CH_CSR_DATA3_VAL 32'hffffffff
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment