modules/*/trigger*/: add backplane trigger debug port

This is useful for debugging if the trigger from a backplane is being acquired correctly.

modules//trigger/: add backplane trigger debug port
This is useful for debugging if the trigger from a backplane is being acquired correctly.
4021144f · Lucas Russo · d24ce23c · 4021144f · 4021144f · 4021144f
Commit 4021144f authored May 20, 2016 by Lucas Russo
5 changed files
--- a/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
@@ -2377,7 +2377,12 @@ package dbe_wishbone_pkg is
      -------------------------------

      trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
-      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0)
+      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0);
+
+      -------------------------------
+      ---- Debug ports
+      -------------------------------
+      trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
    );
  end component;

@@ -2416,7 +2421,12 @@ package dbe_wishbone_pkg is
      -----------------------------

      trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
-      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0)
+      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0);
+
+      -------------------------------
+      ---- Debug ports
+      -------------------------------
+      trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
    );
  end component;

@@ -2487,7 +2497,12 @@ package dbe_wishbone_pkg is
    trig_rcv_intern_i   : in  t_trig_channel_array(g_num_mux_interfaces*g_rcv_intern_num-1 downto 0);  -- signals from inside the FPGA that can be used as input at a rcv mux

    trig_pulse_transm_i : in  t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
-    trig_pulse_rcv_o    : out t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0)
+    trig_pulse_rcv_o    : out t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
+
+      -------------------------------
+      ---- Debug ports
+      -------------------------------
+      trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
  );
  end component;

@@ -2542,7 +2557,12 @@ package dbe_wishbone_pkg is
      trig_rcv_intern_i   : in  t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_rcv_intern_num-1 downto 0);  -- signals from inside the FPGA that can be used as input at a rcv mux

      trig_pulse_transm_i : in  t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
-      trig_pulse_rcv_o    : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0)
+      trig_pulse_rcv_o    : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
+
+      -------------------------------
+      ---- Debug ports
+      -------------------------------
+      trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
    );
  end component;


--- a/hdl/modules/dbe_wishbone/wb_trigger/wb_trigger.vhd
+++ b/hdl/modules/dbe_wishbone/wb_trigger/wb_trigger.vhd
@@ -118,7 +118,13 @@ entity wb_trigger is
    trig_rcv_intern_i   : in  t_trig_channel_array(g_num_mux_interfaces*g_rcv_intern_num-1 downto 0);  -- signals from inside the FPGA that can be used as input at a rcv mux

    trig_pulse_transm_i : in  t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
-    trig_pulse_rcv_o    : out t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0)
+    trig_pulse_rcv_o    : out t_trig_channel_array(g_num_mux_interfaces*g_intern_num-1 downto 0);
+
+    -------------------------------
+    ---- Debug ports
+    -------------------------------
+
+    trig_dbg_o          : out std_logic_vector(g_trig_num-1 downto 0)
    );

 end entity wb_trigger;
@@ -168,7 +174,8 @@ begin  -- architecture rtl
      trig_b      => trig_b,
      trig_dir_o  => trig_dir_o,
      trig_out_o  => trig_out_resolved,
-      trig_in_i   => trig_in_resolved
+      trig_in_i   => trig_in_resolved,
+      trig_dbg_o  => trig_dbg_o
    );

  cmp_trigger_resolver : trigger_resolver

--- a/hdl/modules/dbe_wishbone/wb_trigger/xwb_trigger.vhd
+++ b/hdl/modules/dbe_wishbone/wb_trigger/xwb_trigger.vhd
@@ -61,7 +61,13 @@ entity xwb_trigger is
      trig_rcv_intern_i   : in  t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_rcv_intern_num-1 downto 0);  -- signals from inside the FPGA that can be used as input at a rcv mux

      trig_pulse_transm_i : in  t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
-      trig_pulse_rcv_o    : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0)
+      trig_pulse_rcv_o    : out t_trig_channel_array2d(g_num_mux_interfaces-1 downto 0, g_intern_num-1 downto 0);
+
+    -------------------------------
+    ---- Debug ports
+    -------------------------------
+
+    trig_dbg_o          : out std_logic_vector(g_trig_num-1 downto 0)
    );

 end xwb_trigger;
@@ -142,7 +148,8 @@ begin

      trig_rcv_intern_i   => trig_rcv_intern_compat,
      trig_pulse_transm_i => trig_pulse_transm_compat,
-      trig_pulse_rcv_o    => trig_pulse_rcv_compat
+      trig_pulse_rcv_o    => trig_pulse_rcv_compat,
+      trig_dbg_o          => trig_dbg_o
    );

  gen_wb_slv_trigger_interfaces : for i in 0 to g_num_mux_interfaces-1 generate

--- a/hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
+++ b/hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
@@ -100,7 +100,12 @@ entity wb_trigger_iface is
    -------------------------------

    trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
-    trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0)
+    trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0);
+
+    -------------------------------
+    ---- Debug ports
+    -------------------------------
+    trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
    );

 end entity wb_trigger_iface;
@@ -521,6 +526,8 @@ begin  -- architecture rtl
        t  => ch_regs_out(i).ch_ctl_dir -- 3-state enable input, high=input, low=output
        );

+    trig_dbg_o(i) <= extended_rcv(i);
+
    --------------------------------
    -- Pulse counters
    --------------------------------

--- a/hdl/modules/dbe_wishbone/wb_trigger_iface/xwb_trigger_iface.vhd
+++ b/hdl/modules/dbe_wishbone/wb_trigger_iface/xwb_trigger_iface.vhd
@@ -45,7 +45,12 @@ entity xwb_trigger_iface is
      -----------------------------

      trig_out_o : out t_trig_channel_array(g_trig_num-1 downto 0);
-      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0)
+      trig_in_i  : in  t_trig_channel_array(g_trig_num-1 downto 0);
+
+    -------------------------------
+    ---- Debug ports
+    -------------------------------
+      trig_dbg_o : out std_logic_vector(g_trig_num-1 downto 0)
      );

 end xwb_trigger_iface;
@@ -81,7 +86,8 @@ begin
      trig_b      => trig_b,
      trig_dir_o  => trig_dir_o,
      trig_out_o  => trig_out_o,
-      trig_in_i   => trig_in_i
+      trig_in_i   => trig_in_i,
+      trig_dbg_o  => trig_dbg_o
    );

 end rtl;