Skip to content

B
Beam Positoning Monitor - Gateware
Commit 41b30686 authored by Lucas Russo's avatar Lucas Russo
Browse files
Options

modules/*/wb_fmc_adc_common: add new MMCM reset register field 

This will be used manually reset the ADC MMCM
by software, every time a clock change happens.
parent 7b7fb313
Hide whitespace changes
Inline Side-by-side
Showing with 76 additions and 31 deletions
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/doc/fmc_adc_common_regs_wb.html
View file @ 41b30686
...@@ -411,7 +411,24 @@ wb_fmc_adc_common_csr_monitor_led3_o ...@@ -411,7 +411,24 @@ wb_fmc_adc_common_csr_monitor_led3_o
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
wb_fmc_adc_common_csr_monitor_reserved_i[27:0] wb_fmc_adc_common_csr_monitor_mmcm_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
wb_fmc_adc_common_csr_monitor_reserved_i[26:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&lArr; &lArr;
...@@ -1025,7 +1042,7 @@ MONITOR ...@@ -1025,7 +1042,7 @@ MONITOR
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20] RESERVED[26:19]
</td> </td>
<td > <td >
...@@ -1079,7 +1096,7 @@ RESERVED[27:20] ...@@ -1079,7 +1096,7 @@ RESERVED[27:20]
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12] RESERVED[18:11]
</td> </td>
<td > <td >
...@@ -1133,7 +1150,7 @@ RESERVED[19:12] ...@@ -1133,7 +1150,7 @@ RESERVED[19:12]
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4] RESERVED[10:3]
</td> </td>
<td > <td >
...@@ -1186,8 +1203,11 @@ RESERVED[11:4] ...@@ -1186,8 +1203,11 @@ RESERVED[11:4]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=4 class="td_field"> <td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[3:0] RESERVED[2:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MMCM_RST
</td> </td>
<td style="border: solid 1px black;" colspan=1 class="td_field"> <td style="border: solid 1px black;" colspan=1 class="td_field">
LED3 LED3
...@@ -1206,9 +1226,6 @@ TEST_DATA_EN ...@@ -1206,9 +1226,6 @@ TEST_DATA_EN
</td> </td>
<td > <td >
</td>
<td >
</td> </td>
</tr> </tr>
</table> </table>
...@@ -1230,6 +1247,10 @@ LED3 ...@@ -1230,6 +1247,10 @@ LED3
</b>[<i>read/write</i>]: Led 3 </b>[<i>read/write</i>]: Led 3
<br>FMC LED3 (green) - trigger status indicator<br>0 - LED off - LED on <br>FMC LED3 (green) - trigger status indicator<br>0 - LED off - LED on
<li><b> <li><b>
MMCM_RST
</b>[<i>read/write</i>]: MMCM reset
<br>write 1: reset MMCM.<br> write 0: no effect
<li><b>
RESERVED RESERVED
</b>[<i>read-only</i>]: Reserved </b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's. <br>Ignore on read, write with 0's.
......
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/wb_fmc_adc_common_regs.h
View file @ 41b30686
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : wb_fmc_adc_common_regs.h * File : wb_fmc_adc_common_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb * Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
* Created : Mon Apr 18 09:02:33 2016 * Created : Fri Jul 21 13:54:07 2017
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
...@@ -79,11 +79,14 @@ ...@@ -79,11 +79,14 @@
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */ /* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1) #define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: MMCM reset in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */ /* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28) #define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4 #define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 5
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28) #define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28) #define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* [0x0]: REG Status register */ /* [0x0]: REG Status register */
#define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000 #define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */ /* [0x4]: REG Trigger control */
......
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/wb_fmc_adc_common_regs.vhd
View file @ 41b30686
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wb_fmc_adc_common_regs.vhd -- File : wb_fmc_adc_common_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb -- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
-- Created : Mon Apr 18 09:02:33 2016 -- Created : Fri Jul 21 13:54:07 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
...@@ -44,6 +44,7 @@ signal wb_fmc_adc_common_csr_monitor_test_data_en_int : std_logic ; ...@@ -44,6 +44,7 @@ signal wb_fmc_adc_common_csr_monitor_test_data_en_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led1_int : std_logic ; signal wb_fmc_adc_common_csr_monitor_led1_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led2_int : std_logic ; signal wb_fmc_adc_common_csr_monitor_led2_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led3_int : std_logic ; signal wb_fmc_adc_common_csr_monitor_led3_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_mmcm_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0); signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0); signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0); signal wrdata_reg : std_logic_vector(31 downto 0);
...@@ -78,6 +79,7 @@ begin ...@@ -78,6 +79,7 @@ begin
wb_fmc_adc_common_csr_monitor_led1_int <= '0'; wb_fmc_adc_common_csr_monitor_led1_int <= '0';
wb_fmc_adc_common_csr_monitor_led2_int <= '0'; wb_fmc_adc_common_csr_monitor_led2_int <= '0';
wb_fmc_adc_common_csr_monitor_led3_int <= '0'; wb_fmc_adc_common_csr_monitor_led3_int <= '0';
wb_fmc_adc_common_csr_monitor_mmcm_rst_int <= '0';
elsif rising_edge(clk_sys_i) then elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register -- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1); ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
...@@ -118,12 +120,14 @@ begin ...@@ -118,12 +120,14 @@ begin
wb_fmc_adc_common_csr_monitor_led1_int <= wrdata_reg(1); wb_fmc_adc_common_csr_monitor_led1_int <= wrdata_reg(1);
wb_fmc_adc_common_csr_monitor_led2_int <= wrdata_reg(2); wb_fmc_adc_common_csr_monitor_led2_int <= wrdata_reg(2);
wb_fmc_adc_common_csr_monitor_led3_int <= wrdata_reg(3); wb_fmc_adc_common_csr_monitor_led3_int <= wrdata_reg(3);
wb_fmc_adc_common_csr_monitor_mmcm_rst_int <= wrdata_reg(4);
end if; end if;
rddata_reg(0) <= wb_fmc_adc_common_csr_monitor_test_data_en_int; rddata_reg(0) <= wb_fmc_adc_common_csr_monitor_test_data_en_int;
rddata_reg(1) <= wb_fmc_adc_common_csr_monitor_led1_int; rddata_reg(1) <= wb_fmc_adc_common_csr_monitor_led1_int;
rddata_reg(2) <= wb_fmc_adc_common_csr_monitor_led2_int; rddata_reg(2) <= wb_fmc_adc_common_csr_monitor_led2_int;
rddata_reg(3) <= wb_fmc_adc_common_csr_monitor_led3_int; rddata_reg(3) <= wb_fmc_adc_common_csr_monitor_led3_int;
rddata_reg(31 downto 4) <= regs_i.monitor_reserved_i; rddata_reg(4) <= wb_fmc_adc_common_csr_monitor_mmcm_rst_int;
rddata_reg(31 downto 5) <= regs_i.monitor_reserved_i;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when others => when others =>
...@@ -158,6 +162,8 @@ begin ...@@ -158,6 +162,8 @@ begin
regs_o.monitor_led2_o <= wb_fmc_adc_common_csr_monitor_led2_int; regs_o.monitor_led2_o <= wb_fmc_adc_common_csr_monitor_led2_int;
-- Led 3 -- Led 3
regs_o.monitor_led3_o <= wb_fmc_adc_common_csr_monitor_led3_int; regs_o.monitor_led3_o <= wb_fmc_adc_common_csr_monitor_led3_int;
-- MMCM reset
regs_o.monitor_mmcm_rst_o <= wb_fmc_adc_common_csr_monitor_mmcm_rst_int;
-- Reserved -- Reserved
rwaddr_reg <= wb_adr_i; rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i); wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
......
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/wb_fmc_adc_common_regs.wb
View file @ 41b30686
...@@ -139,12 +139,23 @@ peripheral { ...@@ -139,12 +139,23 @@ peripheral {
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "MMCM reset";
description = "write 1: reset MMCM.\
write 0: no effect";
prefix = "mmcm_rst";
-- Pulse to start
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field { field {
name = "Reserved"; name = "Reserved";
description = "Ignore on read, write with 0's."; description = "Ignore on read, write with 0's.";
prefix = "reserved"; prefix = "reserved";
type = SLV; type = SLV;
size = 28; size = 27;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
......
hdl/modules/dbe_wishbone/wb_fmc_adc_common/wbgen/wb_fmc_adc_common_regs_pkg.vhd
View file @ 41b30686
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : wb_fmc_adc_common_regs_pkg.vhd -- File : wb_fmc_adc_common_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb -- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
-- Created : Mon Apr 18 09:02:33 2016 -- Created : Fri Jul 21 13:54:07 2017
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
...@@ -15,19 +15,19 @@ use ieee.std_logic_1164.all; ...@@ -15,19 +15,19 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
package wb_fmc_adc_common_csr_wbgen2_pkg is package wb_fmc_adc_common_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave) -- Input registers (user design -> WB slave)
type t_wb_fmc_adc_common_csr_in_registers is record type t_wb_fmc_adc_common_csr_in_registers is record
fmc_status_mmcm_locked_i : std_logic; fmc_status_mmcm_locked_i : std_logic;
fmc_status_pwr_good_i : std_logic; fmc_status_pwr_good_i : std_logic;
fmc_status_prst_i : std_logic; fmc_status_prst_i : std_logic;
fmc_status_reserved_i : std_logic_vector(27 downto 0); fmc_status_reserved_i : std_logic_vector(27 downto 0);
trigger_reserved_i : std_logic_vector(28 downto 0); trigger_reserved_i : std_logic_vector(28 downto 0);
monitor_reserved_i : std_logic_vector(27 downto 0); monitor_reserved_i : std_logic_vector(26 downto 0);
end record; end record;
constant c_wb_fmc_adc_common_csr_in_registers_init_value: t_wb_fmc_adc_common_csr_in_registers := ( constant c_wb_fmc_adc_common_csr_in_registers_init_value: t_wb_fmc_adc_common_csr_in_registers := (
fmc_status_mmcm_locked_i => '0', fmc_status_mmcm_locked_i => '0',
fmc_status_pwr_good_i => '0', fmc_status_pwr_good_i => '0',
...@@ -36,9 +36,9 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is ...@@ -36,9 +36,9 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
trigger_reserved_i => (others => '0'), trigger_reserved_i => (others => '0'),
monitor_reserved_i => (others => '0') monitor_reserved_i => (others => '0')
); );
-- Output registers (WB slave -> user design) -- Output registers (WB slave -> user design)
type t_wb_fmc_adc_common_csr_out_registers is record type t_wb_fmc_adc_common_csr_out_registers is record
trigger_dir_o : std_logic; trigger_dir_o : std_logic;
trigger_term_o : std_logic; trigger_term_o : std_logic;
...@@ -47,8 +47,9 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is ...@@ -47,8 +47,9 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
monitor_led1_o : std_logic; monitor_led1_o : std_logic;
monitor_led2_o : std_logic; monitor_led2_o : std_logic;
monitor_led3_o : std_logic; monitor_led3_o : std_logic;
monitor_mmcm_rst_o : std_logic;
end record; end record;
constant c_wb_fmc_adc_common_csr_out_registers_init_value: t_wb_fmc_adc_common_csr_out_registers := ( constant c_wb_fmc_adc_common_csr_out_registers_init_value: t_wb_fmc_adc_common_csr_out_registers := (
trigger_dir_o => '0', trigger_dir_o => '0',
trigger_term_o => '0', trigger_term_o => '0',
...@@ -56,7 +57,8 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is ...@@ -56,7 +57,8 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
monitor_test_data_en_o => '0', monitor_test_data_en_o => '0',
monitor_led1_o => '0', monitor_led1_o => '0',
monitor_led2_o => '0', monitor_led2_o => '0',
monitor_led3_o => '0' monitor_led3_o => '0',
monitor_mmcm_rst_o => '0'
); );
function "or" (left, right: t_wb_fmc_adc_common_csr_in_registers) return t_wb_fmc_adc_common_csr_in_registers; function "or" (left, right: t_wb_fmc_adc_common_csr_in_registers) return t_wb_fmc_adc_common_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic; function f_x_to_zero (x:std_logic) return std_logic;
...@@ -80,8 +82,8 @@ if(x(i) = 'X' or x(i) = 'U') then ...@@ -80,8 +82,8 @@ if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0'; tmp(i):= '0';
else else
tmp(i):=x(i); tmp(i):=x(i);
end if; end if;
end loop; end loop;
return tmp; return tmp;
end function; end function;
function "or" (left, right: t_wb_fmc_adc_common_csr_in_registers) return t_wb_fmc_adc_common_csr_in_registers is function "or" (left, right: t_wb_fmc_adc_common_csr_in_registers) return t_wb_fmc_adc_common_csr_in_registers is
......
hdl/sim/regs/wb_fmc_adc_common_regs.vh
View file @ 41b30686
...@@ -25,5 +25,7 @@ ...@@ -25,5 +25,7 @@
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2 32'h00000004 `define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2 32'h00000004
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3_OFFSET 3 `define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3_OFFSET 3
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 32'h00000008 `define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 32'h00000008
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_OFFSET 4 `define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST_OFFSET 4
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED 32'hfffffff0 `define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST 32'h00000010
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_OFFSET 5
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED 32'hffffffe0
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment