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Beam Positoning Monitor - Gateware
Commit 44bcd6f7 authored by José Alvim Berkenbrock's avatar José Alvim Berkenbrock
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testbench/rffe/: add rffe testbench 

minicircuits gain ctrl testbench added
parent 825fac9e
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hdl/testbench/others/rffe/bpm_gain_ctrl/Manifest.py 0 → 100755
View file @ 44bcd6f7
action = "simulation"
target = "xilinx"
files = ["mc_serial_ctrl_tb.vhd"];
modules = {"local" : [ "../../../../modules/rffe_top/bpm_gain_ctrl" ]};
hdl/testbench/others/rffe/bpm_gain_ctrl/mc_serial_ctrl_tb.vhd 0 → 100755
View file @ 44bcd6f7
------------------------------------------------------------------------------
-- Title : Minicircuits Serial Controller Testbench
------------------------------------------------------------------------------
-- Author : Daniel de Oliveira Tavares
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simulation of mc_serial_ctrl with 100101 as data_i
-- and g_clkdiv = 17 as divider of clk_i.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-01-12 1.0 daniel.tavares Created
-- 2012-10-16 1.1 jose.berkenbrock Names Adpated
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mc_serial_ctrl_tb is
end mc_serial_ctrl_tb;
architecture behavior of mc_serial_ctrl_tb is
-- component Declaration for the Unit Under Test (UUT)
component mc_serial_ctrl
generic(
g_nbits : natural := 6;
g_clkdiv : natural := 128
);
port(
clk_i : in std_logic;
trg_i : in std_logic;
data_i : in std_logic_vector(5 downto 0);
clk_o : out std_logic;
data_o : out std_logic;
le_o : out std_logic
);
end component;
--inputs
signal clk_i : std_logic := '0';
signal trg_i : std_logic := '0';
signal data_i : std_logic_vector(5 downto 0) := (others => '0');
--outputs
signal clk_o : std_logic;
signal data_o : std_logic;
signal le_o : std_logic;
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- instantiate the Unit Under Test (UUT)
uut: mc_serial_ctrl
generic map (
g_clkdiv => 17
)
port map (
clk_i => clk_i,
trg_i => trg_i,
data_i => data_i,
clk_o => clk_o,
data_o => data_o,
le_o => le_o
);
-- Clock process definitions
p_clk_i :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
p_stim: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_i_period*10;
-- insert stimulus here
trg_i <= '1';
data_i <= "100101";
wait for clk_i_period;
trg_i <= '0';
wait;
end process;
end;
hdl/testbench/others/rffe/bpm_swap_ctrl/Manifest.py 0 → 100755
View file @ 44bcd6f7
action = "simulation"
target = "xilinx"
files = ["rf_ch_swap_tb.vhd"];
modules = {"local" : [ "../../../../modules/rffe_top/bpm_swap_ctrl" ]};
hdl/testbench/others/rffe/bpm_swap_ctrl/rf_ch_swap_tb.vhd 0 → 100755
View file @ 44bcd6f7
------------------------------------------------------------------------------
-- Title : RF channels Swapping Testbench
------------------------------------------------------------------------------
-- Author : Jos Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simulation of rf_ch_swap desing behavior.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-18 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rf_ch_swap_tb is
end rf_ch_swap_tb;
architecture behavior of rf_ch_swap_tb is
-- component Declaration for the Unit Under Test (UUT)
component rf_ch_swap
generic(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010");
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
ctrl_o : out std_logic_vector(7 downto 0));
end component;
--inputs
signal clk_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal en_swap_i : std_logic := '0';
signal mode_i : std_logic_vector(1 downto 0) := (others => '0');
--outputs
signal ctrl_o : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 8 ns;
constant en_period : time := 80 ns;
begin
-- instantiate the Unit Under Test (UUT)
uut: rf_ch_swap
port map (
clk_i => clk_i,
rst_i => rst_i,
en_swap_i => en_swap_i,
mode_i => mode_i,
ctrl_o => ctrl_o
);
-- Clock process definitions
p_clock :process
begin
clk_i <= '1';
wait for clk_period/2;
clk_i <= '0';
wait for clk_period/2;
end process;
p_enable :process
begin
en_swap_i <= '1';
wait for en_period/2;
en_swap_i <= '0';
wait for en_period/2;
end process;
-- Stimulus process
p_stim: process
begin
-- hold reset state for 16 ns.
rst_i <= '1';
wait for clk_period*2;
rst_i <= '0';
wait for clk_period*14;
-- insert stimulus here
rst_i <= '0';
mode_i <= "11";
wait for clk_period*44;
-- Another reset period
rst_i <= '1';
wait for clk_period*20;
-- insert stimulus here
rst_i <= '0';
mode_i <= "11";
wait for clk_period*22;
mode_i <= "01";
wait for clk_period*30;
mode_i <= "11";
wait for clk_period*22;
-- Another reset period
rst_i <= '1';
wait for clk_period*14;
-- insert stimulus here
rst_i <= '0';
wait for clk_period*44;
mode_i <= "10";
wait for clk_period*5;
wait;
end process;
end;
\ No newline at end of file
hdl/testbench/others/rffe/bpm_swap_ctrl/wave.wcfg 0 → 100755
View file @ 44bcd6f7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="numeric_std" />
<top_module name="rf_ch_swap_tb" />
<top_module name="std_logic_1164" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="10" />
<wvobject fp_name="/rf_ch_swap_tb/clk_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk_i</obj_property>
<obj_property name="ObjectShortName">clk_i</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/rst_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst_i</obj_property>
<obj_property name="ObjectShortName">rst_i</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/en_swap_i" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">en_swap_i</obj_property>
<obj_property name="ObjectShortName">en_swap_i</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/mode_i" type="array" db_ref_id="1">
<obj_property name="ElementShortName">mode_i[1:0]</obj_property>
<obj_property name="ObjectShortName">mode_i[1:0]</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/uut/s_ctrl" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_ctrl[7:0]</obj_property>
<obj_property name="ObjectShortName">s_ctrl[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/ctrl_o" type="array" db_ref_id="1">
<obj_property name="ElementShortName">ctrl_o[7:0]</obj_property>
<obj_property name="ObjectShortName">ctrl_o[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/en_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">en_period</obj_property>
<obj_property name="ObjectShortName">en_period</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/uut/g_direct" type="array" db_ref_id="1">
<obj_property name="ElementShortName">g_direct[7:0]</obj_property>
<obj_property name="ObjectShortName">g_direct[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/rf_ch_swap_tb/uut/g_inverted" type="array" db_ref_id="1">
<obj_property name="ElementShortName">g_inverted[7:0]</obj_property>
<obj_property name="ObjectShortName">g_inverted[7:0]</obj_property>
</wvobject>
</wave_config>
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