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Beam Positoning Monitor - Gateware
Commit 458a91f9 authored by Lucas Russo's avatar Lucas Russo
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hdl/*: small fixes

parent f29097a7
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Showing with 115 additions and 58 deletions
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
View file @ 458a91f9
......@@ -32,8 +32,6 @@ use work.fmc150_wbgen2_pkg.all;
-- Reset Synch
use work.custom_common_pkg.all;
-- FIX. Test SOF and EOF in wb_source_out at the same sycle. Should work.
entity wb_fmc150 is
generic
(
......
hdl/modules/custom_wishbone/wb_irq_mngr/wb_irq_mngr.vhd
View file @ 458a91f9
......@@ -14,41 +14,41 @@ use work.wishbone_pkg.all;
use work.gencores_pkg.all;
entity wb_irq_mngr is
generic(
g_irq_count : integer := 16;
g_irq_level : std_logic := '1';
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
generic(
g_irq_count : integer := 16;
g_irq_level : std_logic := '1';
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- Global Signals
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone interface signals
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--slave_i : in t_wishbone_slave_in;
--slave_o : out t_wishbone_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--slave_i : in t_wishbone_slave_in;
--slave_o : out t_wishbone_slave_out;
-- irq from other IP
irq_req_i : in std_logic_vector(g_irq_count-1 downto 0);
-- Component external signals
irq_req_o : out std_logic
);
-- irq from other IP
irq_req_i : in std_logic_vector(g_irq_count-1 downto 0);
-- Component external signals
irq_req_o : out std_logic
);
end wb_irq_mngr;
architecture rtl of wb_irq_mngr is
-- Read/Write regs
constant c_IRQ_REG_MASK : std_logic_vector(2 downto 0) := "000"; -- *reg* IRQ mask
constant c_IRQ_REG_MASK : std_logic_vector(2 downto 0) := "000"; -- *reg* IRQ mask
constant c_IRQ_REG_ACK : std_logic_vector(2 downto 0) := "001"; -- *reg* IRQ acknowledge from master
-- Read regs
......@@ -172,15 +172,15 @@ begin
wr_ack <= '0';
-- WB WRITE classic cycle. Word granularity
if(wb_in.stb = '1' and wb_in.we = '0' and wb_in.cyc = '1' and sel = '1') then
wr_ack <= '1';
if(wb_in.adr(4 downto 2) = c_IRQ_REG_MASK) then
irq_mask <= wb_in.dat(g_irq_count-1 downto 0);
elsif(wb_in.adr(4 downto 2) = c_IRQ_REG_ACK) then
irq_ack <= wb_in.dat(g_irq_count-1 downto 0);
end if;
if(wb_in.stb = '1' and wb_in.we = '0' and wb_in.cyc = '1' and sel = '1') then
wr_ack <= '1';
if(wb_in.adr(4 downto 2) = c_IRQ_REG_MASK) then
irq_mask <= wb_in.dat(g_irq_count-1 downto 0);
elsif(wb_in.adr(4 downto 2) = c_IRQ_REG_ACK) then
irq_ack <= wb_in.dat(g_irq_count-1 downto 0);
end if;
end if;
end if;
end if;
end process;
irq_req_o <= g_irq_level when(unsigned(irq_pend) /= 0 and rst_n_i = '1') else
......
hdl/syn/dbe_bpm_simple/_impact.log 0 → 100644
View file @ 458a91f9
iMPACT Version: 13.4
iMPACT log file Started on Tue Oct 23 16:50:50 2012
Welcome to iMPACT
iMPACT Version: 13.4
// *** BATCH CMD : loadProjectFile -file "/home/lerwys/impact/dbe_proj.ipf"
INFO:iMPACT - Failed to open file: -- File ? --, replace with 'bypass'.
INFO:iMPACT:1777 -
Reading /opt/Xilinx/13.4/ISE_DS/ISE/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
'2': Loading file'/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bit' ...
done.
INFO:iMPACT:1777 -
Reading /opt/Xilinx/13.4/ISE_DS/ISE/virtex6/data/xc6vlx240t.bsd...
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '2': Added Device xc6vlx240t successfully.
----------------------------------------------------------------------
Active mode is BS
// *** BATCH CMD : setMode -ss
// *** BATCH CMD : setMode -sm
// *** BATCH CMD : setMode -hw140
// *** BATCH CMD : setMode -spi
// *** BATCH CMD : setMode -acecf
// *** BATCH CMD : setMode -acempm
// *** BATCH CMD : setMode -pff
// *** BATCH CMD : setMode -bs
Project: '/home/lerwys/impact/dbe_proj.ipf' loaded.
GUI --- Auto connect to cable...
// *** BATCH CMD : setCable -port auto
INFO:iMPACT - Digilent Plugin: no JTAG device was found.
AutoDetecting cable. Please wait.
PROGRESS_START - Starting Operation.
Cable is LOCKED. Retrying...
The cable is being used by another application.
Please try opening the cable connection at a later time.
Connecting to cable (Parallel Port - parport0).
Linux release = 3.2.0-32-generic.
WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648.
Cable connection failed.
Connecting to cable (Parallel Port - parport1).
Linux release = 3.2.0-32-generic.
WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648.
Cable connection failed.
Connecting to cable (Parallel Port - parport2).
Linux release = 3.2.0-32-generic.
WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648.
Cable connection failed.
Connecting to cable (Parallel Port - parport3).
Linux release = 3.2.0-32-generic.
WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648.
Cable connection failed.
PROGRESS_END - End Operation.
Elapsed time = 13 sec.
Cable autodetection failed.
WARNING:iMPACT:923 - Can not find cable, check cable setup !
\ No newline at end of file
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.gise
View file @ 458a91f9
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1351016887">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4142841353681478520" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-4142841353681478520" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8648913000068208811" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8648913000068208811" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3190671188300613176" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3190671188300613176" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="15701343915878886" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="15701343915878886" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587252" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="4353560571877669279" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351016888" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="4353560571877669279" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587377" xil_pn:in_ck="-3676352999506393327" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4204764714131478187" xil_pn:start_ts="1350587252">
<transform xil_pn:end_ts="1351017026" xil_pn:in_ck="-3676352999506393327" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="4204764714131478187" xil_pn:start_ts="1351016888">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1350587377" xil_pn:in_ck="1309770857089352171" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6566612260269040355" xil_pn:start_ts="1350587377">
<transform xil_pn:end_ts="1351017026" xil_pn:in_ck="1309770857089352171" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6566612260269040355" xil_pn:start_ts="1351017026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1350587404" xil_pn:in_ck="4181690111764201426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8990626865624946785" xil_pn:start_ts="1350587377">
<transform xil_pn:end_ts="1351017053" xil_pn:in_ck="4181690111764201426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8990626865624946785" xil_pn:start_ts="1351017026">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="dbe_bpm_simple_top.ngd"/>
<outfile xil_pn:name="dbe_bpm_simple_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1350587564" xil_pn:in_ck="-956280685729320234" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="5939692501008836605" xil_pn:start_ts="1350587404">
<transform xil_pn:end_ts="1351017208" xil_pn:in_ck="-956280685729320234" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="5939692501008836605" xil_pn:start_ts="1351017053">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="dbe_bpm_simple_top_summary.xml"/>
<outfile xil_pn:name="dbe_bpm_simple_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1350587722" xil_pn:in_ck="-4414935198573544209" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="6734387949470617483" xil_pn:start_ts="1350587564">
<transform xil_pn:end_ts="1351017363" xil_pn:in_ck="-4414935198573544209" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="6734387949470617483" xil_pn:start_ts="1351017208">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="dbe_bpm_simple_top_pad.txt"/>
<outfile xil_pn:name="dbe_bpm_simple_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1350587855" xil_pn:in_ck="1577483878535902759" xil_pn:name="TRANEXT_bitFile_virtex6" xil_pn:prop_ck="8799862395714727328" xil_pn:start_ts="1350587722">
<transform xil_pn:end_ts="1351017495" xil_pn:in_ck="1577483878535902759" xil_pn:name="TRANEXT_bitFile_virtex6" xil_pn:prop_ck="8799862395714727328" xil_pn:start_ts="1351017363">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +170,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1350587722" xil_pn:in_ck="-956280685729320366" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1350587691">
<transform xil_pn:end_ts="1351017363" xil_pn:in_ck="-956280685729320366" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416183" xil_pn:start_ts="1351017333">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bgn
View file @ 458a91f9
......@@ -6,7 +6,7 @@ Loading device for application Rf_Device from file '6vlx240t.nph' in environment
ff1156, speed -1
Opened constraints file dbe_bpm_simple_top.pcf.
Thu Oct 18 16:15:37 2012
Tue Oct 23 16:36:18 2012
/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:2 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g Disable_JTAG:No -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ConfigFallback:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g USR_ACCESS:None -g next_config_addr:None -g JTAG_SysMon:Enable -g DCIUpdateMode:Quiet -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No dbe_bpm_simple_top.ncd
......@@ -150,22 +150,22 @@ There were 0 CONFIG constraint(s) processed from dbe_bpm_simple_top.pcf.
Running DRC.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring4_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring2_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring5_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring1_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring2_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/oserdes_clock
with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4.
......
hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd
View file @ 458a91f9
......@@ -400,7 +400,7 @@ begin
cmp_xwb_fmc150 : xwb_fmc150
generic map(
g_interface_mode => CLASSIC,
g_address_granularity => WORD
g_address_granularity => BYTE
--g_packet_size => 32,
--g_sim => 0
)
......
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