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Commit 46b14fbd authored by Lucas Russo's avatar Lucas Russo
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emb-sw/*: add interface to some fmc516 chips

parent 7ec28c04
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embedded-sw/fmc/fmc.mk 0 → 100644
View file @ 46b14fbd
ifdef CONFIG_FMC150
OBJS_FMC150 += fmc/fmc150/fmc150.o
endif
ifdef CONFIG_FMC516
OBJS_FMC516 += fmc/fmc516/lmk02000.o fmc/fmc516/isla216p25.o fmc/fmc516/fmc516.o
endif
OBJS_FMC += $(OBJS_FMC150) $(OBJS_FMC516)
embedded-sw/fmc/fmc150/fmc150.c 0 → 100644
View file @ 46b14fbd
#include "board.h"
#include "inttypes.h"
#include "fmc150.h"
// Delay in number of processor clock cycles
#define SPI_DELAY 300
#define SPI_BUSY_MAX_TRIES 10
/* Register values for cdce72010 */
uint32_t cdce72010_regs[CDCE72010_NUMREGS] = {
//internal reference clock. Default config.
/*0x683C0310,
0x68000021,
0x83040002,
0x68000003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68050CC9,
0x05FC270A,
0x0280044B,
0x0000180C*/
//3.84MHz ext clock. Does not lock.
/*0x682C0290,
0x68840041,
0x83840002,
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000C49,
0x0BFC02FA,
0x8000050B,
0x0000180C*/
//61.44MHz ext clock. LOCK.
/*0x682C0290,
0x68840041,
0x83040002,
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x0024009A,
0x8000050B,
0x0000180C*/
//7.68MHz ext clock. Lock.
// Use with Libera RF & clock generator. RF = 291.840MHz, MCf = 7.680MHz, H = 38
// DDS = 3.072MHz -> Phase increment = 2048d
0x682C0290,
0x68840041,
0x83860002, //divide by 5
//0x83840002, //divide by 4
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x007C003A, // PFD_freq = 1.92MHz
0x8000050B,
//0x0000180C
//15.36MHz ext clock.
/*0x682C0290,
0x68840041,
0x83840002,
/*;83020002,;divide by 6
;83860002, ;divide by 5
;83800002, ;divide by 2
;83840002, ;divide by 4
;83060002, ;divide by 8
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x003C003A,
0x8000050B,
0x0000180C*/
//9.6MHz ext clock.
/*0x682C0290,
0x68840041,
0x83860002,//;divide by 5
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x007C004A,
0x8000050B,
0x0000180C*/
//9.250MHz ext clock. No lock
/*0x682C0290,
0x68840041,
0x83860002,
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x5FFC39CA,
//0x8000390B, // DIvide by 32
0x8000050B, //Divide by 8
0x0000180C*/
//10.803 (originally 10.803 actually) ext clock.
//Could it be something related to the lock window? see cdce72010 datasheet
/*0x682C0290,
0x68840041,
0x83840002,
0x68400003,
0xE9800004,
0x68000005,
0x68000006,
0x83800017,
0x68000098,
0x68000049,
0x03FC02CA,
0x8000050B,
0x0000180C*/
};
// Global FMC150 handler.
fmc150_t *fmc150;
int fmc150_init(void)
{
if (fmc150_devl->devices){
// get first gpio device found
fmc150 = (fmc150_t *)fmc150_devl->devices->base;//BASE_FMC150;
return 0;
}
return -1;
}
void update_fmc150_adc_delay(uint8_t adc_strobe_delay, uint8_t adc_cha_delay, uint8_t adc_chb_delay)
{
fmc150->ADC_DLY = (uint32_t) FMC150_ADC_DLY_STR_W(adc_strobe_delay) +
(uint32_t) FMC150_ADC_DLY_CHA_W(adc_cha_delay) +
(uint32_t) FMC150_ADC_DLY_CHB_W(adc_chb_delay);
fmc150->FLGS_PULSE = 0x1;
}
/* Check if 150 is busy */
int fmc150_spi_busy(void)
{
return fmc150->FLGS_OUT & FMC150_FLGS_OUT_SPI_BUSY;
}
int read_fmc150_register(uint32_t cs, uint32_t addr, uint32_t* data)
{
// Test if SPI interface is busy
if (fmc150_spi_busy())
return -1;
// Set bit to read from SPI
fmc150->FLGS_IN |= FMC150_FLGS_IN_SPI_RW;
// Set address to read from
fmc150->ADDR = addr;
// Toggle chipselect
fmc150->CS ^= cs;
// Sleeps SPI_DELAY*4 processor cycles. Is that enough? */
delay(SPI_DELAY);
// Get data from register
*data = fmc150->DATA_OUT;
return 0;
}
int write_fmc150_register(uint32_t cs, uint32_t addr, uint32_t data)
{
// Test if SPI interface is busy
if (fmc150_spi_busy())
return -1;
// Set bit to write from SPI
fmc150->FLGS_IN &= ~FMC150_FLGS_IN_SPI_RW;
// Set address to write to
fmc150->ADDR = addr;
// Set value to write to
fmc150->DATA_IN = data;
// Toggle chipselect
fmc150->CS ^= cs;
return 0;
}
static int fmc150_spi_busy_loop()
{
int i = 0;
for(i = 0; i < SPI_BUSY_MAX_TRIES; ++i){
if(!fmc150_spi_busy())
break;
delay(SPI_DELAY);
}
// return error (-1) if max tries reached
if (i == SPI_BUSY_MAX_TRIES)
return -1;
else
return 0;
}
// TODO: implement a register structure and associate permissions
// (RO, RW, WO)
int init_cdce72010()
{
int i;
uint32_t reg;
/* Write regs to cdce72010 statically */
// Do not write the last register, as it is Read-only
for(i = 0; i < CDCE72010_NUMREGS; ++i){
if(fmc150_spi_busy_loop() < 0){
pp_printf("init_cdce72010: max SPI tries excceded!\n");
return -1;
}
pp_printf("init_cdce72010: writing data: 0x%x at register addr: 0x%x\n", cdce72010_regs[i], i);
// The CDCE72010 chip word addressed , hence the "i" addressing index
write_fmc150_register(FMC150_CS_CDCE72010, i, cdce72010_regs[i]);
// Do a write-read cycle in order to ensure that we wrote the correct value
delay(SPI_DELAY);
if(fmc150_spi_busy_loop() < 0){
pp_printf("init_cdce72010: max SPI tries excceded!\n");
return -1;
}
// The CDCE72010 chip word addressed , hence the "i" addressing index
read_fmc150_register(FMC150_CS_CDCE72010, i, &reg);
pp_printf("init_cdce72010: reading data: 0x%x at register addr: 0x%x\n", reg, i);
// Check if value written is the same of the value just read
if(cdce72010_regs[i] != reg){
pp_printf("init_cdce72010: error: data written (0x%x) != data read (0x%x)!\n",
cdce72010_regs[i], reg);
return -1;
}
delay(SPI_DELAY);
}
return 0;
}
embedded-sw/fmc/fmc516/fmc516.c 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "memmgr.h"
#include "fmc516.h"
// Global UART handler.
fmc516_t **fmc516;
int fmc516_init(void)
{
int i;
struct dev_node *dev_p = 0;
if (!fmc516_devl->devices)
return -1;
// get all base addresses
fmc516 = (fmc516_t **) memmgr_alloc(sizeof(fmc516_t *)*fmc516_devl->size);
for (i = 0, dev_p = fmc516_devl->devices; i < fmc516_devl->size;
++i, dev_p = dev_p->next) {
fmc516[i] = (fmc516_t *) dev_p->base;
// Initialize fmc516 components
dbg_print("> initilizing fmc516 regs\n");
fmc516_init_regs(i);
dbg_print("> initilizing fmc516 lmk02000\n");
fmc516_lmk02000_init();
dbg_print("> initilizing fmc516 isla216\n");
fmc516_isla216_all_init();
dbg_print("> fmc516 addr[%d]: %08X\n", i, dev_p->base);
}
dbg_print("> fmc516 size: %d\n", fmc516_devl->size);
//fmc516 = (fmc516_t *)fmc516_devl->devices->base;//BASE_FMC516;
return 0;
}
int fmc516_exit()
{
// free fmc516 structure
memmgr_free(fmc516);
return 0;
}
// For now just ta few registers are initialized
void fmc516_init_regs(unsigned int id)
{
uint32_t fmc516_reg = 0;
dbg_print("> fmc516_init_regs...\n");
// No test data. External reference on. Led0 on. Led1 on. VCXO off
fmc516_reg |= FMC516_FMC_CTL_CLK_SEL |
FMC516_FMC_CTL_LED_0;
//FMC516_FMC_CTL_LED_0;
fmc516[id]->FMC_CTL = fmc516_reg;
}
void fmc516_clk_sel(unsigned int id, int ext_clk)
{
if (ext_clk)
fmc516[id]->FMC_CTL |= FMC516_FMC_CTL_CLK_SEL;
}
void fmc516_led0(unsigned int id, int on)
{
if (on)
fmc516[id]->FMC_CTL |= FMC516_FMC_CTL_LED_0;
}
void fmc516_led1(unsigned int id, int on)
{
if (on)
fmc516[id]->FMC_CTL |= FMC516_FMC_CTL_LED_1;
}
embedded-sw/fmc/fmc516/isla216p25.c 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "isla216p25.h"
#include "isla216p25_regs.h"
/*
* Which SPI ID is isla216p25? See board.h for definitions.
* Should be dynamically detected...
*/
static void fmc516_isla216_load_regset(const struct default_dev_regs_t *regs, int ss);
static void fmc516_isla216_write_instaddr_raw(uint32_t val, int ss);
static void fmc516_isla216_readw_raw(uint32_t *val, int ss);
static void fmc516_isla216_writew_raw(uint32_t val, int ss);
int fmc516_isla216_all_init()
{
int i;
for (i = 0; i < FMC516_NUM_ISLA216; ++i)
fmc516_isla216_load_regset(isla216p25_regs_default, i);
return 0;
}
int fmc516_isla216_init(int ss)
{
fmc516_isla216_load_regset(isla216p25_regs_default, ss);
return 0;
}
// isla216p25 has 16 bits for instruction/address: addr(13)+length(2)+rw(1)
static void fmc516_isla216_write_instaddr_raw(uint32_t val, int ss)
{
// three-wire mode
oc_spi_three_mode_tx(FMC516_ISLA216P25_SPI_ID, ss,
FMC516_ISLA216_INSTADDR_SIZE, val);
}
static void fmc516_isla216_readw_raw(uint32_t *val, int ss)
{
// three-wire mode
oc_spi_three_mode_rx(FMC516_ISLA216P25_SPI_ID, ss,
FMC516_ISLA216_WORD_SIZE, val);
}
static void fmc516_isla216_writew_raw(uint32_t val, int ss)
{
// three-wire mode
oc_spi_three_mode_tx(FMC516_ISLA216P25_SPI_ID, ss,
FMC516_ISLA216_WORD_SIZE, val);
}
void fmc516_isla216_write_instaddr(int addr, int length, int read, int ss)
{
oc_spi_txrx(FMC516_LMK02000_SPI_ID, FMC516_LMK02000_CS,
FMC516_LMK02000_SIZE, val, NULL);
}
// No readback is available for lmk02000
/*
int fmc516_lmk02000_read_reg(int addr)
{
}
*/
uint32_t fmc516_isla216_reg;
// 1-byte length
fmc516_isla216_reg = FMC516_ISLA216_ADDR(addr) |
FMC516_ISLA216_LENGTH(length-1);
if (read)
fmc516_isla216_reg |= FMC516_ISLA216_READ;
fmc516_isla216_write_instaddr_raw(fmc516_isla216_reg, ss);
}
// word is 8-bit (1 byte) long for isla216p25
int fmc516_isla216_read_byte(int addr, int ss)
{
uint32_t val;
fmc516_isla216_write_instaddr(addr, 1, 1, ss);
// Read the desired byte
fmc516_isla216_readw_raw(&val, ss);
return val & 0xff;
}
void fmc516_isla216_write_byte(int val, int addr, int ss)
{
fmc516_isla216_write_instaddr(addr, 1, 0, ss);
// Write the desired byte
fmc516_isla216_writew_raw(val, ss);
}
// Read up to 4 bytes
int fmc516_isla216_read_n(int addr, int length, int ss)
{
int i;
int ret = 0;
int mask = 0;
uint32_t fmc516_isla216_val;
// n-byte length
fmc516_isla216_write_instaddr(addr, length, 1, ss);
// Read the desired bytes
for (i = 0; i < length; ++i) {
fmc516_isla216_readw_raw(&fmc516_isla216_val, ss);
ret |= (fmc516_isla216_val & 0xff) << 8*i;
mask |= (0xff << 8*i);
}
return ret & mask;
}
// Write up to 4 bytes
void fmc516_isla216_write_n(int val, int addr, int length, int ss)
{
int i;
// n-byte length
fmc516_isla216_write_instaddr(addr, length, 0, ss);
// Write the desired bytes
for (i = 0; i < length; ++i) {
fmc516_isla216_writew_raw(val >> 8*i, ss);
}
}
static void fmc516_isla216_load_regset(const struct default_dev_regs_t *regs, int ss)
{
int i = 0;
while (regs[i].type != REGS_DEFAULT_END){
fmc516_isla216_write_byte(regs[i].val, regs[i].addr, ss);
++i;
}
}
/*
* Specififc ISLA216P Functions
*/
int fmc516_isla216_chkcal_stat(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CALSTATUS_REG, ss) & ISLA216_CALDONE_MASK;
}
void fmc516_isla216_test_ramp(int ss)
{
fmc516_isla216_write_byte(ISLA216_OUT_TESTMODE(ISLA216_OUT_TESTIO_RAMP),
ISLA216_TESTIO_REG, ss);
}
int fmc516_isla216_get_chipid(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CHIPID_REG, ss) & ISLA216_CHIPID_MASK;
}
int fmc516_isla216_get_chipver(int ss)
{
return fmc516_isla216_read_byte(ISLA216_CHIPVER_REG, ss) & ISLA216_CHIPVER_MASK;
}
embedded-sw/fmc/fmc516/lmk02000.c 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "debug_print.h"
#include "lmk02000.h"
#include "lmk02000_regs.h"
/*
* Which SPI ID is lmk02000? See board.h for definitions.
* Should be dynamically detected...
*/
static void fmc516_lmk02000_load_regset(const struct default_dev_regs_t *regs);
int fmc516_lmk02000_init(void)
{
dbg_print("> fmc516_lmk02000_init...\n");
fmc516_lmk02000_load_regset(lmk02000_regs_default);
return 0;
}
// lmk02000 has 28 msb value and 4 lsb addr
void fmc516_lmk02000_write_reg(int val)
{
dbg_print("> fmc516_lmk02000_write_reg...\n");
oc_spi_txrx(FMC516_LMK02000_SPI_ID, FMC516_LMK02000_CS,
FMC516_LMK02000_SIZE, val, 0);
}
// No readback is available for lmk02000
/*
int fmc516_lmk02000_read_reg(int addr)
{
}
*/
static void fmc516_lmk02000_load_regset(const struct default_dev_regs_t *regs)
{
int i = 0;
dbg_print("> fmc516_lmk02000_load_regset...\n");
while (regs[i].type != REGS_DEFAULT_END){
dbg_print("> fmc516_lmk02000_load_regset while: %d...\n", i);
fmc516_lmk02000_write_reg(regs[i].val);
++i;
}
}
embedded-sw/include/board.h 0 → 120000
View file @ 46b14fbd
../boards/ml605/board.h
\ No newline at end of file
embedded-sw/include/fmc/fmc516/fmc516.h 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "debug_print.h"
#include "hw/wb_fmc516.h"
#include "isla216p25.h"
#include "lmk02000.h"
#define DEFAULT_FMC516_ID 0
/* Type definitions */
typedef volatile struct FMC516_WB fmc516_t;
int fmc516_init(void);
int fmc516_exit(void);
// For now just ta few registers are initialized
void fmc516_init_regs(unsigned int id);
void fmc516_clk_sel(unsigned int id, int ext_clk);
void fmc516_led0(unsigned int id, int ext_clk);
void fmc516_led1(unsigned int id, int ext_clk);
embedded-sw/include/fmc/fmc516/isla216p25.h 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "regs.h"
#define FMC516_ISLA216_ADC0 0
#define FMC516_ISLA216_ADC1 1
#define FMC516_ISLA216_ADC2 2
#define FMC516_ISLA216_ADC3 3
#define FMC516_NUM_ISLA216 4
#define FMC516_ISLA216_RW_SIZE 1
#define FMC516_ISLA216_RW_OFS 0
#define FMC516_ISLA216_RW_MASK 0x1
#define FMC516_ISLA216_RW(x) (((x) << FMC516_ISLA216_RW_OFS) & FMC516_ISLA216_RW_MASK)
#define FMC516_ISLA216_READ (FMC516_ISLA216_RW(1))
//#define FMC516_ISLA216_WRITE (~FMC516_ISLA216_READ)
#define FMC516_ISLA216_LENGTH_SIZE 2
#define FMC516_ISLA216_LENGTH_OFS 1
#define FMC516_ISLA216_LENGTH_MASK 0x6
#define FMC516_ISLA216_LENGTH(x) (((x) << FMC516_ISLA216_LENGTH_OFS) & FMC516_ISLA216_LENGTH_MASK)
#define FMC516_ISLA216_ADDR_SIZE 13
#define FMC516_ISLA216_ADDR_OFS 3
#define FMC516_ISLA216_ADDR_MASK 0xFFF8
#define FMC516_ISLA216_ADDR(x) (((x) << FMC516_ISLA216_ADDR_OFS) & FMC516_ISLA216_ADDR_MASK)
#define FMC516_ISLA216_INSTADDR_SIZE (FMC516_ISLA216_RW_SIZE + \
FMC516_ISLA216_LENGTH_SIZE + \
FMC516_ISLA216_ADDR_SIZE)
#define FMC516_ISLA216_WORD_SIZE 8
/*
* Internal ISLA216P register description from ISLA216P25
* datasheet Incomplete! Byte addressed!
*/
#define ISLA216_PORTCONFIG_REG 0x00000000
//#define ISLA216_RES0_REG 0x00000001
#define SPI_REG_BURSTEND_REG 0x00000002
//#define ISLA216_RES1_REG 0x00000003
//#define ISLA216_RES2_REG 0x00000004
//#define ISLA216_RES3_REG 0x00000005
//#define ISLA216_RES4_REG 0x00000006
//#define ISLA216_RES5_REG 0x00000007
#define ISLA216_CHIPID_REG 0x00000008
#define ISLA216_CHIPID_MASK 0xff
#define ISLA216_CHIPVER_REG 0x00000009
#define ISLA216_CHIPVER_MASK 0xff
//#define ISLA216_RES6_REG 0x0000000a
//#define ISLA216_RES7_REG 0x0000000b
//#define ISLA216_RES8_REG 0x0000000c
//#define ISLA216_RES9_REG 0x0000000d
//#define ISLA216_RES10_REG 0x0000000e
//#define ISLA216_RES11_REG 0x0000000f
//
//#define ISLA216_RES12_REG 0x00000010
//#define ISLA216_RES13_REG 0x00000011
//#define ISLA216_RES14_REG 0x00000012
//#define ISLA216_RES15_REG 0x00000013
//#define ISLA216_RES16_REG 0x00000014
//#define ISLA216_RES17_REG 0x00000015
//#define ISLA216_RES18_REG 0x00000016
//#define ISLA216_RES19_REG 0x00000017
//#define ISLA216_RES20_REG 0x00000018
//#define ISLA216_RES21_REG 0x00000019
//#define ISLA216_RES22_REG 0x0000001a
//#define ISLA216_RES23_REG 0x0000001b
//#define ISLA216_RES24_REG 0x0000001c
//#define ISLA216_RES25_REG 0x0000001d
//#define ISLA216_RES26_REG 0x0000001e
//#define ISLA216_RES27_REG 0x0000001f
#define ISLA216_MODESADC0_REG 0x00000025
#define ISLA216_MODESADC1_REG 0x0000002b
#define ISLA216_CLKDIV_REG 0x00000072
#define ISLA216_OUTMODEA_REG 0x00000073
#define ISLA216_OUTFMT_MASK 0x00000007
#define ISLA216_OUTFMT_OFS 0
#define ISLA216_OUTFMT(x) (((x) << ISLA216_OUTFMT_OFS) & ISLA216_OUTFMT_MASK)
#define ISLA216_OUTFMT_2COMPL 0
#define ISLA216_OUTFMT_GRAYCODE (1<<1)
#define ISLA216_OUTFMT_OFSBIN (1<<2)
#define ISLA216_OUTMODE_MASK 0x000000E0
#define ISLA216_OUTMODE_OFS 4
#define ISLA216_OUTMODE(x) (((x) << ISLA216_OUTMODE_OFS) & ISLA216_OUTMODE_MASK)
#define ISLA216_OUTMODE_LVDS3 0
#define ISLA216_OUTMODE_LVDS2 1
#define ISLA216_OUTMODE_LVCMOS (1<<2)
#define ISLA216_OUTMODEB_REG 0x00000074
#define ISLA216_CALSTATUS_REG 0x000000b6
#define ISLA216_CALDONE_MASK 0x1
#define ISLA216_TESTIO_REG 0x000000C0
#define ISLA216_USR_TESTMODE_MASK 0x00000007
#define ISLA216_USR_TESTMODE_OFS 0
#define ISLA216_USR_TESTMODE(x) (((x) << ISLA216_USR_TESTMODE_OFS) & ISLA216_USR_TESTMODE_MASK)
#define ISLA216_USR_TESTIO_USRPAT1 0
#define ISLA216_USR_TESTIO_CYCPAT13 1
#define ISLA216_USR_TESTIO_CYCPAT135 2
#define ISLA216_USR_TESTIO_CYCPAT1357 3
#define ISLA216_OUT_TESTMODE_MASK 0x000000f0
#define ISLA216_OUT_TESTMODE_OFS 4
#define ISLA216_OUT_TESTMODE(x) (((x) << ISLA216_OUT_TESTMODE_OFS) & ISLA216_OUT_TESTMODE_MASK)
#define ISLA216_OUT_TESTIO_OFF 0
#define ISLA216_OUT_TESTIO_MIDSHORT 1
#define ISLA216_OUT_TESTIO_PLUS_FSSHORT 2
#define ISLA216_OUT_TESTIO_MINUS_FSSHORT 3
#define ISLA216_OUT_TESTIO_RES0 4
#define ISLA216_OUT_TESTIO_RES1 5
#define ISLA216_OUT_TESTIO_RES2 6
#define ISLA216_OUT_TESTIO_RES3 7
#define ISLA216_OUT_TESTIO_USRPAT 8
#define ISLA216_OUT_TESTIO_RES4 9
#define ISLA216_OUT_TESTIO_RAMP 10
#define ISLA216_OUT_TESTIO_RES5 11
#define ISLA216_OUT_TESTIO_RES6 12
#define ISLA216_OUT_TESTIO_RES7 13
#define ISLA216_OUT_TESTIO_RES8 14
#define ISLA216_OUT_TESTIO_RES9 15
/*
* ISLA216P Functions
*/
int fmc516_isla216_init(int ss);
int fmc516_isla216_all_init(void);
void fmc516_isla216_write_instaddr(int addr, int length, int read, int ss);
// word is 8-bit (1 byte) long for isla216p25
int fmc516_isla216_read_byte(int addr, int ss);
void fmc516_isla216_write_byte(int val, int addr, int ss);
// Read up to 4 bytes
int fmc516_isla216_read_n(int addr, int length, int ss);
// Write up to 4 bytes
void fmc516_isla216_write_n(int val, int addr, int length, int ss);
/*
* Convinient ISLA216P Functions
*/
int fmc516_isla216_chkcal_stat(int ss);
void fmc516_isla216_test_ramp(int ss);
int fmc516_isla216_get_chipid(int ss);
int fmc516_isla216_get_chipver(int ss);
embedded-sw/include/fmc/fmc516/isla216p25_regs.h 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include "regs.h"
// isla216p25 has 8-bit value and 13-bit register address
const struct default_dev_regs_t isla216p25_regs_default[] =
{
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 31 },
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 8 },
{REGS_DEFAULT_NO_INIT, 4, 0x1, 0 },
{REGS_DEFAULT_INIT, 4, 0x2, (1<<16)|(1<<8)|2 },
{REGS_DEFAULT_NO_INIT, 4, 0x3, 0 },
{REGS_DEFAULT_INIT, 4, 0x4, (1<<16)|(1<<8)| 4 },
{REGS_DEFAULT_INIT, 4, 0x5, (1<<16)|(1<<8)| 5 },
{REGS_DEFAULT_INIT, 4, 0x6, (1<<16)|(1<<8)| 6 },
{REGS_DEFAULT_INIT, 4, 0x7, (1<<16)|(1<<8)| 7 },
/*
{REGS_TYPE_RESERVED, 4, 0x8, 0 },
{REGS_TYPE_RESERVED, 4, 0x9, 0 },
{REGS_TYPE_RESERVED, 4, 0xa, 0 },
*/
{REGS_DEFAULT_NO_INIT, 4, 0xb, 0 },
/*
{REGS_TYPE_RESERVED, 4, 0xc, 0 },
{REGS_TYPE_RESERVED, 4, 0xd, 0 },
*/
{REGS_DEFAULT_INIT, 4, 0xe, 0x2b100100|14 },
{REGS_DEFAULT_NO_INIT, 4, 0xf, 0x4003e800|15 },
{REGS_DEFAULT_END, 0, 0 , 0 }
};
embedded-sw/include/fmc/fmc516/lmk02000.h 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <inttypes.h>
#include "board.h" // Board definitions: SPI device structure
#include "spi.h" // SPI device functions
#include "regs.h"
#define FMC516_LMK02000_CS 0
#define FMC516_LMK02000_VAL_SIZE 28
#define FMC516_LMK02000_VAL_OFS 4
#define FMC516_LMK02000_ADDR_SIZE 4
#define FMC516_LMK02000_ADDR_OFS 0
#define FMC516_LMK02000_SIZE (FMC516_LMK02000_VAL_SIZE + FMC516_LMK02000_ADDR_SIZE)
int fmc516_lmk02000_init(void);
// lmk02000 has 28 msb value and 4 lsb addr
void fmc516_lmk02000_write_reg(int val);
embedded-sw/include/fmc/fmc516/lmk02000_regs.h 0 → 100644
View file @ 46b14fbd
/*
* Copyright (C) 2013 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include "regs.h"
// lmk02000 has 28 msb value and 4 lsb addr
const struct default_dev_regs_t lmk02000_regs_default[] =
{
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 31 },
{REGS_DEFAULT_INIT, 4, 0x0, 1 << 8 },
{REGS_DEFAULT_NO_INIT, 4, 0x1, 0 },
{REGS_DEFAULT_INIT, 4, 0x2, (1<<16)|(1<<8)|2 },
{REGS_DEFAULT_NO_INIT, 4, 0x3, 0 },
{REGS_DEFAULT_INIT, 4, 0x4, (1<<16)|(1<<8)| 4 },
{REGS_DEFAULT_INIT, 4, 0x5, (1<<16)|(1<<8)| 5 },
{REGS_DEFAULT_INIT, 4, 0x6, (1<<16)|(1<<8)| 6 },
{REGS_DEFAULT_INIT, 4, 0x7, (1<<16)|(1<<8)| 7 },
/*
{REGS_TYPE_RESERVED, 4, 0x8, 0 },
{REGS_TYPE_RESERVED, 4, 0x9, 0 },
{REGS_TYPE_RESERVED, 4, 0xa, 0 },
*/
{REGS_DEFAULT_NO_INIT, 4, 0xb, 0 },
/*
{REGS_TYPE_RESERVED, 4, 0xc, 0 },
{REGS_TYPE_RESERVED, 4, 0xd, 0 },
*/
{REGS_DEFAULT_INIT, 4, 0xe, 0x2b100100|14 },
{REGS_DEFAULT_NO_INIT, 4, 0xf, 0x4003e800|15 },
{REGS_DEFAULT_END, 0, 0 , 0 }
};
embedded-sw/include/hw/wb_fmc516.h 0 → 100644
View file @ 46b14fbd
This diff is collapsed.
embedded-sw/include/spi.h
View file @ 46b14fbd
......@@ -17,18 +17,12 @@ int spi_init(void);
void spi_exit(void);
int oc_spi_poll(unsigned int id);
void oc_spi_config(unsigned int id, int ass, int rx_neg, int tx_neg,
<<<<<<< HEAD
int lsb, int ie);
=======
int lsb, int ie);
// For use only with spi three-wire mode
int oc_spi_three_mode_tx(unsigned int id, int ss, int nbits, uint32_t in)
// For use only with spi three-wire mode
int oc_spi_three_mode_rx(unsigned int id, int ss, int nbits, uint32_t *out)
<<<<<<< HEAD
>>>>>>> e8e9b7f... various: temp-mess 4
=======
>>>>>>> e8e9b7f... various: temp-mess 4
int oc_spi_txrx(unsigned int id, int ss, int nbits, uint32_t in, uint32_t *out);
......
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