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Beam Positoning Monitor - Gateware
Commit 47e5d27e authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_acq_core_mux/*: update interface as wb_acq_core changed

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hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
View file @ 47e5d27e
......@@ -96,6 +96,7 @@ port
acq_val_low_array_i : in t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
acq_val_high_array_i : in t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
acq_dvalid_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
acq_id_array_i : in t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
acq_trig_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
-----------------------------
......@@ -274,6 +275,7 @@ begin
acq_val_low_i => acq_val_low_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
acq_val_high_i => acq_val_high_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
acq_dvalid_i => acq_dvalid_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
acq_id_i => acq_id_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
acq_trig_i => acq_trig_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
-----------------------------
......
hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux_plain.vhd
View file @ 47e5d27e
......@@ -90,6 +90,7 @@ port
acq_val_low_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels*c_acq_chan_width-1 downto 0);
acq_val_high_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels*c_acq_chan_width-1 downto 0);
acq_dvalid_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
acq_id_array_i : in unsigned(g_acq_num_cores*g_acq_num_channels*c_acq_id_width-1 downto 0);
acq_trig_array_i : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
-----------------------------
......@@ -166,6 +167,7 @@ architecture rtl of wb_acq_core_mux_plain is
signal acq_val_low_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_val_high_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_dvalid_array : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_id_array : t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_trig_array : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
begin
......@@ -224,6 +226,7 @@ begin
acq_val_low_array_i => acq_val_low_array,
acq_val_high_array_i => acq_val_high_array,
acq_dvalid_array_i => acq_dvalid_array,
acq_id_array_i => acq_id_array,
acq_trig_array_i => acq_trig_array,
-----------------------------
......@@ -302,6 +305,8 @@ begin
acq_val_high_array(i*g_acq_num_channels+j) <=
acq_val_high_array_i(i*g_acq_num_channels*c_acq_chan_width + c_acq_chan_width*(j+1)-1 downto i*g_acq_num_channels*c_acq_chan_width + c_acq_chan_width*j);
acq_dvalid_array(i*g_acq_num_channels+j) <= acq_dvalid_array_i(i*g_acq_num_channels+j);
acq_id_array(i*g_acq_num_channels+j) <=
acq_id_array_i(i*g_acq_num_channels*c_acq_id_width + c_acq_id_width*(j+1)-1 downto i*g_acq_num_channels*c_acq_id_width + c_acq_id_width*j);
acq_trig_array(i*g_acq_num_channels+j) <= acq_trig_array_i(i*g_acq_num_channels+j);
end generate;
......
hdl/modules/dbe_wishbone/wb_acq_core_mux/xwb_acq_core_mux.vhd
View file @ 47e5d27e
......@@ -125,6 +125,7 @@ architecture rtl of xwb_acq_core_mux is
signal acq_val_low_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_val_high_array : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_dvalid_array : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_id_array : t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal acq_trig_array : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
signal wb_adr_array_in : std_logic_vector(g_acq_num_cores*c_wishbone_address_width-1 downto 0);
......@@ -195,6 +196,7 @@ begin
acq_val_low_array_i => acq_val_low_array,
acq_val_high_array_i => acq_val_high_array,
acq_dvalid_array_i => acq_dvalid_array,
acq_id_array_i => acq_id_array,
acq_trig_array_i => acq_trig_array,
-----------------------------
......@@ -287,6 +289,7 @@ begin
acq_val_low_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).val_low;
acq_val_high_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).val_high;
acq_dvalid_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).dvalid;
acq_id_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).id;
acq_trig_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).trig;
end generate;
......
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