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Beam Positoning Monitor - Gateware
Commit 48a98478 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'wb-fmc516-devel' into dsp-devel 

Conflicts:
	embedded-sw/dbe_main.c
	hdl/syn/loader/impact.batch
parents 91de5701 2b973368
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embedded-sw/dbe.vhd
View file @ 48a98478
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embedded-sw/dbe_lwip.vhd 0 → 100644
View file @ 48a98478
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embedded-sw/dbe_main.c
View file @ 48a98478
......@@ -459,6 +459,11 @@ void fmc516_test()
// pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
//}
for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
fmc516_isla216_test_ramp(i);
pp_printf("> FMC516_ISLA216_ADC%d: ramp test enabled!\n", i);
}
//for (i = 0; i < FMC516_NUM_ISLA216; ++i) {
// fmc516_isla216_test_midscale(i);
// pp_printf("> FMC516_ISLA216_ADC%d: test miscale enabled!\n", i);
......
embedded-sw/fmc/fmc516/fmc516.c
View file @ 48a98478
......@@ -71,9 +71,9 @@ void fmc516_init_regs(unsigned int id)
dbg_print("> Leds and clock select\n");
// No test data. External reference on. Led0 on. Led1 on. VCXO off
// No test data. External reference on. Led0 on. VCXO off
fmc516_clk_sel(id, 1);
fmc516_led1(id, 1);
fmc516_led0(id, 1);
// Adjsut the delays of all channels. Don't change these values
// unless you really have to!
......
etherbone-core @ 541e5b83
Subproject commit 66a04ccc2516c81e5f51a34ba188e8bfc1d41671
Subproject commit 541e5b834123ad6a86325edf607c885069706f3f
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd
View file @ 48a98478
......@@ -404,14 +404,14 @@ package custom_wishbone_pkg is
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
--sys_spi_data_b : inout std_logic;
sys_spi_dout_o : out std_logic;
sys_spi_din_i : in std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o : out std_logic;
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
......@@ -450,6 +450,7 @@ package custom_wishbone_pkg is
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
--adc_data_ch1_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
--adc_data_ch2_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
......@@ -557,14 +558,14 @@ package custom_wishbone_pkg is
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
--sys_spi_data_b : inout std_logic;
sys_spi_dout_o : out std_logic;
sys_spi_din_i : in std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o : out std_logic;
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
......@@ -603,6 +604,7 @@ package custom_wishbone_pkg is
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
--adc_data_ch1_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
--adc_data_ch2_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
......
hdl/modules/custom_wishbone/wb_fmc516/fmc516_adc_clk.vhd
View file @ 48a98478
......@@ -251,22 +251,21 @@ begin
-- resourses guide page 53, note 2)
--COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
--DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT_F => 12.000,
--CLKFBOUT_MULT_F => 8.000,
--DIVCLK_DIVIDE => 4,
DIVCLK_DIVIDE => 2,
--CLKFBOUT_MULT_F => 12.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
-- adc clock
CLKOUT0_DIVIDE_F => 3.000,
--CLKOUT0_DIVIDE_F => 4.000,
--CLKOUT0_DIVIDE_F => 3.000,
CLKOUT0_DIVIDE_F => 4.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
-- 2x adc clock. This should not be 2x. FIX
--CLKOUT1_DIVIDE => 2,
CLKOUT1_DIVIDE => 3,
--CLKOUT1_DIVIDE => 4,
-- 2x adc clock.
--CLKOUT1_DIVIDE => 3,
CLKOUT1_DIVIDE => 2,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
......
hdl/modules/custom_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ 48a98478
......@@ -121,14 +121,14 @@ port
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
--sys_spi_data_b : inout std_logic;
sys_spi_dout_o : out std_logic;
sys_spi_din_i : in std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o : out std_logic;
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic := '0';
......@@ -167,6 +167,7 @@ port
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
--adc_data_ch1_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
--adc_data_ch2_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
......@@ -1060,6 +1061,7 @@ begin
-- Output ADC signals to external FPGA
adc_clk_o <= fs_clk;
adc_clk2x_o <= fs_clk2x;
adc_data_o <= adc_data;
adc_data_valid_o <= adc_valid;
......@@ -1180,9 +1182,11 @@ begin
-- Output SPI clock
sys_spi_clk_o <= sys_spi_clk;
sys_spi_dout_o <= sys_spi_dout;
sys_spi_din <= sys_spi_din_i;
sys_spi_miosio_oe_n_o <= sys_spi_miosio_oe_n;
--sys_spi_dout_o <= sys_spi_dout;
--sys_spi_din <= sys_spi_din_i;
sys_spi_data_b <= sys_spi_dout when sys_spi_miosio_oe_n = '0' else 'Z';
sys_spi_din <= sys_spi_data_b;
--sys_spi_miosio_oe_n_o <= sys_spi_miosio_oe_n;
-- Assign slave select lines
sys_spi_cs_adc0_n_o <= sys_spi_ss_int(0); -- SPI ADC CS channel 0
......@@ -1228,7 +1232,7 @@ begin
-- Output latch enable signal
lmk_uwire_latch_en_o <= fmc_lmk_uwire_ss_int(0);
-- ???
-- Deprecated
lmk_sync_o <= '0';
-- Not used wishbone signals
......
hdl/modules/custom_wishbone/wb_fmc516/xwb_fmc516.vhd
View file @ 48a98478
......@@ -99,14 +99,14 @@ port
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o : out std_logic;
--sys_spi_data_b : inout std_logic;
sys_spi_dout_o : out std_logic;
sys_spi_din_i : in std_logic;
sys_spi_data_b : inout std_logic;
--sys_spi_dout_o : out std_logic;
--sys_spi_din_i : in std_logic;
sys_spi_cs_adc0_n_o : out std_logic; -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o : out std_logic; -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o : out std_logic; -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o : out std_logic; -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o : out std_logic;
--sys_spi_miosio_oe_n_o : out std_logic;
-- External Trigger To/From FMC
m2c_trig_p_i : in std_logic;
......@@ -145,6 +145,7 @@ port
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_clk2x_o : out std_logic_vector(c_num_adc_channels-1 downto 0);
adc_data_o : out std_logic_vector(c_num_adc_channels*c_num_adc_bits-1 downto 0);
--adc_data_ch1_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
--adc_data_ch2_o : out std_logic_vector(c_num_adc_bits-1 downto 0);
......@@ -265,14 +266,14 @@ begin
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_o,
--sys_spi_data_b => sys_spi_data_b,
sys_spi_dout_o => sys_spi_dout_o,
sys_spi_din_i => sys_spi_din_i,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_o,
--sys_spi_din_i => sys_spi_din_i,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_o, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_o, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_o, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_o, -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_o,
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_o,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
......@@ -311,6 +312,7 @@ begin
-- ADC output signals. Continuous flow
-----------------------------
adc_clk_o => adc_clk_o,
adc_clk2x_o => adc_clk2x_o,
adc_data_o => adc_data_o,
adc_data_valid_o => adc_data_valid_o,
......
hdl/syn/dbe_bpm_fmc516/make_output
View file @ 48a98478
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/syn/dbe_bpm_fmc516/planAhead_run_1/dbe_bpm_fmc516.ppr 0 → 100644
View file @ 48a98478
<?xml version="1.0"?>
<Project Version="4" Minor="27">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Part" Val="xc6vlx240tff1156-1"/>
<Option Name="TargetLanguage" Val="Verilog"/>
<Option Name="SourceMgmtMode" Val="All"/>
</Config>
</Project>
hdl/syn/dbe_bpm_fmc516/planAhead_run_1/planAhead.jou 0 → 100644
View file @ 48a98478
#-----------------------------------------------------------
# PlanAhead v13.4 (64-bit)
# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011
# Start of session at: Tue Jun 4 09:44:13 2013
# Process ID: 20165
# Log file: /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/planAhead_run_1/planAhead.log
# Journal file: /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui
source /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_fmc516/pa.fromNetlist.tcl
exit
stop_gui
hdl/syn/loader/impact.batch deleted 100755 → 0
View file @ 91de5701
setMode -bscan
setCable -port auto
identify
assignFile -p 2 -file ../dbe_bpm_dsp/dbe_bpm_dsp.bit
program -p 2
closeCable
quit
hdl/syn/loader/program_fpga deleted 100755 → 0
View file @ 91de5701
#!/bin/bash
impact -batch impact.batch
hdl/testbench/others/rffe/bpm_swap_ctrl/Makefile 0 → 100644
View file @ 48a98478
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE :=
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := /opt/Xilinx/13.4/ISE_DS/ISE/vhdl/hdp/lin64
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := rf_ch_swap_tb.vhd \
../../../../modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd \
VHDL_OBJ := work/rf_ch_swap_tb/.rf_ch_swap_tb_vhd \
work/rf_ch_swap/.rf_ch_swap_vhd \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(LIB_IND) xilinxsim.ini
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse: ;
ifeq ($(TOP_MODULE),)
@echo "Environment variable TOP_MODULE not set!"
else
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
endif
clean:
rm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb
.PHONY: clean
work/.work:
(mkdir work && touch work/.work && echo "work=work" >> xilinxsim.ini) || rm -rf work
work/rf_ch_swap_tb/.rf_ch_swap_tb_vhd: rf_ch_swap_tb.vhd work/rf_ch_swap_tb/.rf_ch_swap_tb
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/rf_ch_swap_tb/.rf_ch_swap_tb:
@mkdir -p $(dir $@) && touch $@
work/rf_ch_swap/.rf_ch_swap_vhd: ../../../../modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd work/rf_ch_swap/.rf_ch_swap
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/rf_ch_swap/.rf_ch_swap:
@mkdir -p $(dir $@) && touch $@
hdl/top/ml_605/dbe_bpm_fmc516/chipscope.cpj
View file @ 48a98478
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Apr 16 18:08:29 BRT 2013
#Mon Jun 17 16:36:50 BRT 2013
avoidUserRegDevice1=2,3,4
deviceChain.deviceName0=System_ACE_CF
deviceChain.deviceName1=XC6VLX240T
......@@ -8,8 +8,8 @@ deviceChain.iRLength1=10
deviceChain.name0=MyDevice0
deviceChain.name1=MyDevice1
deviceIds=0a00109364250093
mdiAreaHeight=0.6989374262101535
mdiAreaHeightLast=0.6989374262101535
mdiAreaHeight=0.7060773480662983
mdiAreaHeightLast=0.6718232044198895
mdiCount=10
mdiDevice0=1
mdiDevice1=1
......@@ -24,27 +24,27 @@ mdiDevice9=1
mdiType0=5
mdiType1=1
mdiType2=2
mdiType3=0
mdiType3=5
mdiType4=0
mdiType5=1
mdiType6=5
mdiType6=0
mdiType7=0
mdiType8=0
mdiType9=1
mdiUnit0=0
mdiUnit0=1
mdiUnit1=0
mdiUnit2=0
mdiUnit3=0
mdiUnit4=1
mdiUnit5=1
mdiUnit6=1
mdiUnit6=0
mdiUnit7=2
mdiUnit8=3
mdiUnit9=3
navigatorHeight=0.1782762691853601
navigatorHeightLast=0.1782762691853601
navigatorWidth=0.17897371714643304
navigatorWidthLast=0.17897371714643304
navigatorHeight=0.1712707182320442
navigatorHeightLast=0.1712707182320442
navigatorWidth=0.17852684144818975
navigatorWidthLast=0.17852684144818975
signalDisplayPath=0
unit.-1.-1.username=
unit.1.-1.coretype=SYSTEM MONITOR
......@@ -52,25 +52,25 @@ unit.1.-1.port.-1.buscount=0
unit.1.-1.port.-1.channelcount=0
unit.1.-1.portcount=0
unit.1.-1.username=
unit.1.0.0.HEIGHT0=0.48726654
unit.1.0.0.HEIGHT0=0.4638365
unit.1.0.0.TriggerRow0=1
unit.1.0.0.TriggerRow1=1
unit.1.0.0.TriggerRow2=1
unit.1.0.0.WIDTH0=1.0
unit.1.0.0.WIDTH0=0.99769586
unit.1.0.0.X0=0.0
unit.1.0.0.Y0=0.0
unit.1.0.1.HEIGHT1=0.5670628
unit.1.0.1.WIDTH1=1.0
unit.1.0.1.HEIGHT1=0.5393082
unit.1.0.1.WIDTH1=0.99769586
unit.1.0.1.X1=0.0
unit.1.0.1.Y1=0.3803056
unit.1.0.2.HEIGHT2=0.39219016
unit.1.0.2.WIDTH2=0.92604005
unit.1.0.2.X2=0.07395994
unit.1.0.2.Y2=0.55348045
unit.1.0.5.HEIGHT5=0.93718165
unit.1.0.5.WIDTH5=0.95069337
unit.1.0.5.X5=0.049306627
unit.1.0.5.Y5=0.008488964
unit.1.0.1.Y1=0.3616352
unit.1.0.2.HEIGHT2=0.3726415
unit.1.0.2.WIDTH2=0.9239631
unit.1.0.2.X2=0.07373272
unit.1.0.2.Y2=0.5267296
unit.1.0.5.HEIGHT5=0.8915094
unit.1.0.5.WIDTH5=0.9485407
unit.1.0.5.X5=0.049155146
unit.1.0.5.Y5=0.007861636
unit.1.0.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.1.0.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.1.0.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXX0XXXXXXXX
......@@ -96,7 +96,7 @@ unit.1.0.MFEventType0=3
unit.1.0.MFEventType1=3
unit.1.0.MFEventType2=3
unit.1.0.MFEventType3=3
unit.1.0.RunMode=SINGLE RUN
unit.1.0.RunMode=REPETITIVE RUN
unit.1.0.SQCondition=All Data
unit.1.0.SQContiguous0=0
unit.1.0.SequencerOn=0
......@@ -160,10 +160,10 @@ unit.1.0.plotBusX=fmc516_debug_dull
unit.1.0.plotBusY=fmc_rst_adcs_n
unit.1.0.plotDataTimeMode=1
unit.1.0.plotDisplayMode=line
unit.1.0.plotMaxX=583.2878048780487
unit.1.0.plotMaxY=1749.0
unit.1.0.plotMinX=387.52682926829266
unit.1.0.plotMinY=-1598.0
unit.1.0.plotMaxX=0.0
unit.1.0.plotMaxY=0.0
unit.1.0.plotMinX=0.0
unit.1.0.plotMinY=0.0
unit.1.0.plotSelectedBus=3
unit.1.0.port.-1.b.0.alias=fmc516_adc_ch1
unit.1.0.port.-1.b.0.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
......@@ -1828,21 +1828,21 @@ unit.1.0.waveform.posn.9.channel=2147483646
unit.1.0.waveform.posn.9.name=fmc_lmk_lock
unit.1.0.waveform.posn.9.radix=1
unit.1.0.waveform.posn.9.type=bus
unit.1.1.0.HEIGHT0=0.39049235
unit.1.1.0.HEIGHT0=0.3710692
unit.1.1.0.TriggerRow0=1
unit.1.1.0.TriggerRow1=1
unit.1.1.0.TriggerRow2=1
unit.1.1.0.WIDTH0=0.95069337
unit.1.1.0.X0=0.049306627
unit.1.1.0.WIDTH0=0.9485407
unit.1.1.0.X0=0.049155146
unit.1.1.0.Y0=0.0
unit.1.1.1.HEIGHT1=0.84889644
unit.1.1.1.WIDTH1=0.90138674
unit.1.1.1.X1=0.098613255
unit.1.1.1.Y1=0.60780984
unit.1.1.5.HEIGHT5=0.84889644
unit.1.1.5.WIDTH5=0.8767334
unit.1.1.5.X5=0.03312789
unit.1.1.5.Y5=0.061120544
unit.1.1.1.HEIGHT1=0.8081761
unit.1.1.1.WIDTH1=0.8993856
unit.1.1.1.X1=0.09831029
unit.1.1.1.Y1=0.5786164
unit.1.1.5.HEIGHT5=0.8081761
unit.1.1.5.WIDTH5=0.874808
unit.1.1.5.X5=0.033026114
unit.1.1.5.Y5=0.0581761
unit.1.1.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.1.1.MFBitsA1=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unit.1.1.MFBitsA2=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
......@@ -1885,28 +1885,30 @@ unit.1.1.TCOutputEnable0=0
unit.1.1.TCOutputHigh0=1
unit.1.1.TCOutputMode0=0
unit.1.1.browser_tree_state<Data\ Port>=1
unit.1.1.browser_tree_state<fmc_adc_data_ch0>=1
unit.1.1.browser_tree_state<fmc_adc_data_ch3>=0
unit.1.1.coretype=ILA
unit.1.1.eventCount0=1
unit.1.1.eventCount1=1
unit.1.1.eventCount2=1
unit.1.1.eventCount3=1
unit.1.1.plotBusColor0=-16777092
unit.1.1.plotBusColor1=-3407821
unit.1.1.plotBusColor0=-3407821
unit.1.1.plotBusColor1=-16777092
unit.1.1.plotBusCount=2
unit.1.1.plotBusName0=fmc_adc_data_ch3
unit.1.1.plotBusName1=fmc_adc_data_ch0
unit.1.1.plotBusX=fmc_adc_data_ch0
unit.1.1.plotBusY=fmc_adc_data_ch0
unit.1.1.plotBusX=fmc_adc_data_ch3
unit.1.1.plotBusY=fmc_adc_data_ch3
unit.1.1.plotDataTimeMode=1
unit.1.1.plotDisplayMode=line
unit.1.1.plotMaxX=678.826695371367
unit.1.1.plotMaxY=1700.0
unit.1.1.plotMinX=484.8762109795479
unit.1.1.plotMinY=-1572.0
unit.1.1.plotMaxX=0.0
unit.1.1.plotMaxY=0.0
unit.1.1.plotMinX=0.0
unit.1.1.plotMinY=0.0
unit.1.1.plotSelectedBus=3
unit.1.1.port.-1.b.0.alias=fmc_adc_data_ch0
unit.1.1.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
unit.1.1.port.-1.b.0.color=java.awt.Color[r\=204,g\=0,b\=51]
unit.1.1.port.-1.b.0.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
unit.1.1.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.1.port.-1.b.0.name=DataPort
unit.1.1.port.-1.b.0.orderindex=-1
unit.1.1.port.-1.b.0.radix=Signed
......@@ -1919,8 +1921,8 @@ unit.1.1.port.-1.b.0.unsignedPrecision=0
unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0
unit.1.1.port.-1.b.0.visible=1
unit.1.1.port.-1.b.1.alias=fmc_adc_data_ch3
unit.1.1.port.-1.b.1.channellist=16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
unit.1.1.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.1.1.port.-1.b.1.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
unit.1.1.port.-1.b.1.color=java.awt.Color[r\=204,g\=0,b\=51]
unit.1.1.port.-1.b.1.name=DataPort
unit.1.1.port.-1.b.1.orderindex=-1
unit.1.1.port.-1.b.1.radix=Signed
......@@ -3676,12 +3678,12 @@ unit.1.1.waveform.posn.98.type=signal
unit.1.1.waveform.posn.99.channel=127
unit.1.1.waveform.posn.99.name=DataPort[127]
unit.1.1.waveform.posn.99.type=signal
unit.1.2.0.HEIGHT0=0.39049235
unit.1.2.0.HEIGHT0=0.3710692
unit.1.2.0.TriggerRow0=1
unit.1.2.0.TriggerRow1=1
unit.1.2.0.TriggerRow2=1
unit.1.2.0.WIDTH0=0.92604005
unit.1.2.0.X0=0.07395994
unit.1.2.0.WIDTH0=0.9239631
unit.1.2.0.X0=0.07373272
unit.1.2.0.Y0=0.0
unit.1.2.5.HEIGHT5=0.84889644
unit.1.2.5.WIDTH5=0.8520801
......@@ -5100,17 +5102,17 @@ unit.1.2.triggerWindowCount=1
unit.1.2.triggerWindowDepth=4096
unit.1.2.triggerWindowTS=0
unit.1.2.username=MyILA2
unit.1.3.0.HEIGHT0=0.39049235
unit.1.3.0.HEIGHT0=0.3710692
unit.1.3.0.TriggerRow0=1
unit.1.3.0.TriggerRow1=1
unit.1.3.0.TriggerRow2=1
unit.1.3.0.WIDTH0=1.0
unit.1.3.0.WIDTH0=0.99769586
unit.1.3.0.X0=0.0
unit.1.3.0.Y0=0.0
unit.1.3.1.HEIGHT1=0.72156197
unit.1.3.1.WIDTH1=1.0
unit.1.3.1.HEIGHT1=0.6871069
unit.1.3.1.WIDTH1=0.99769586
unit.1.3.1.X1=0.0
unit.1.3.1.Y1=0.27843803
unit.1.3.1.Y1=0.26415095
unit.1.3.5.HEIGHT5=0.84889644
unit.1.3.5.WIDTH5=0.8274268
unit.1.3.5.X5=0.009244992
......
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.ucf
View file @ 48a98478
......@@ -122,16 +122,16 @@ NET "fmc_lmk_lock_o" LOC="AD21" | IOSTANDARD = "LVCMOS25";
# The CLOCK_DEDICATED_ROUTE=FALSE workaround is typically for source clocks which
# are not assigned to global clock input pins
NET "adc_clk0_p_i" TNM_NET = "adc_clk0_p_i" | CLOCK_DEDICATED_ROUTE=FALSE;
NET "adc_clk0_p_i" TNM_NET = "adc_clk0_p_i";
TIMESPEC "TS_adc_clk0_p_i" = PERIOD "adc_clk0_p_i" 4 ns HIGH 50%;
NET "adc_clk1_p_i" TNM_NET = "adc_clk1_p_i" | CLOCK_DEDICATED_ROUTE=FALSE;
NET "adc_clk1_p_i" TNM_NET = "adc_clk1_p_i";
TIMESPEC "TS_adc_clk1_p_i" = PERIOD "adc_clk1_p_i" 4 ns HIGH 50%;
NET "adc_clk2_p_i" TNM_NET = "adc_clk2_p_i" | CLOCK_DEDICATED_ROUTE=FALSE;
NET "adc_clk2_p_i" TNM_NET = "adc_clk2_p_i";
TIMESPEC "TS_adc_clk2_p_i" = PERIOD "adc_clk2_p_i" 4 ns HIGH 50%;
NET "adc_clk3_p_i" TNM_NET = "adc_clk3_p_i" | CLOCK_DEDICATED_ROUTE=FALSE;
NET "adc_clk3_p_i" TNM_NET = "adc_clk3_p_i";
TIMESPEC "TS_adc_clk3_p_i" = PERIOD "adc_clk3_p_i" 4 ns HIGH 50%;
NET "adc_clk0_p_i" LOC = "AP20" | IOSTANDARD = LVDS_25;
......
hdl/top/ml_605/dbe_bpm_fmc516/dbe_bpm_fmc516.vhd
View file @ 48a98478
......@@ -336,6 +336,7 @@ architecture rtl of dbe_bpm_fmc516 is
signal fmc516_lmk_lock_int : std_logic;
signal fmc516_fs_clk : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_fs_clk2x : std_logic_vector(c_num_adc_channels-1 downto 0);
signal fmc516_adc_data : std_logic_vector(c_num_adc_channels*16-1 downto 0);
signal fmc516_adc_valid : std_logic_vector(c_num_adc_channels-1 downto 0);
......@@ -838,15 +839,15 @@ begin
fmc_leds_o => fmc_leds_o,
-- ADC SPI control interface. Three-wire mode. Tri-stated data pin
sys_spi_clk_o => sys_spi_clk_int,--sys_spi_clk_o,
--sys_spi_data_b => sys_spi_data_b,--sys_spi_data_int,
sys_spi_dout_o => sys_spi_dout_int,
sys_spi_din_i => sys_spi_din_int,
sys_spi_clk_o => sys_spi_clk_int,
sys_spi_data_b => sys_spi_data_b,
--sys_spi_dout_o => sys_spi_dout_int,
--sys_spi_din_i => sys_spi_din_int,
sys_spi_cs_adc0_n_o => sys_spi_cs_adc0_n_int, -- SPI ADC CS channel 0
sys_spi_cs_adc1_n_o => sys_spi_cs_adc1_n_int, -- SPI ADC CS channel 1
sys_spi_cs_adc2_n_o => sys_spi_cs_adc2_n_int, -- SPI ADC CS channel 2
sys_spi_cs_adc3_n_o => sys_spi_cs_adc3_n_int, -- SPI ADC CS channel 3
sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
--sys_spi_miosio_oe_n_o => sys_spi_miosio_oe_n_int,
-- External Trigger To/From FMC
m2c_trig_p_i => m2c_trig_p_i,
......@@ -886,6 +887,7 @@ begin
-- ADC output signals. Continuous flow.
-----------------------------
adc_clk_o => fmc516_fs_clk,
adc_clk2x_o => fmc516_fs_clk2x,
adc_data_o => fmc516_adc_data,
adc_data_valid_o => fmc516_adc_valid,
......@@ -894,9 +896,7 @@ begin
-----------------------------
-- Trigger to other FPGA logic
trig_hw_o => open,
--trig_hw_i => '0',
-- DEBUG!
trig_hw_i => fmc_debug,
trig_hw_i => '0',
-- General board status
fmc_mmcm_lock_o => fmc516_mmcm_lock_int,
fmc_lmk_lock_o => fmc516_lmk_lock_int,
......@@ -922,12 +922,10 @@ begin
fmc_lmk_lock_o <= fmc516_lmk_lock_int;
-- Tri-state buffer for SPI three-wire mode
sys_spi_data_b <= sys_spi_dout_int when sys_spi_miosio_oe_n_int = '0' else 'Z';
sys_spi_din_int <= sys_spi_data_b;
--sys_spi_data_b <= sys_spi_dout_int when sys_spi_miosio_oe_n_int = '0' else 'Z';
--sys_spi_din_int <= sys_spi_data_b;
sys_spi_clk_o <= sys_spi_clk_int;
-- Does this work at all?
--sys_spi_data_b <= sys_spi_data_int;
sys_spi_cs_adc0_n_o <= sys_spi_cs_adc0_n_int;
sys_spi_cs_adc1_n_o <= sys_spi_cs_adc1_n_int;
sys_spi_cs_adc2_n_o <= sys_spi_cs_adc2_n_int;
......@@ -941,7 +939,9 @@ begin
-- Reset FMC516 ADCs
fmc_reset_adcs_n_o <= fmc_reset_adcs_n_out;
fmc516_fs_rst_n <= clk_sys_rstn and fmc516_mmcm_lock_int;
--fmc516_fs_rst_n <= clk_sys_rstn and fmc516_mmcm_lock_int;
-- Do not use mmcm_lock as reset.
fmc516_fs_rst_n <= clk_sys_rstn;
p_fmc516_reset_adcs : process(fmc516_fs_clk(c_adc_ref_clk))
begin
......@@ -958,20 +958,20 @@ begin
end if;
end process;
p_debug : process(sys_spi_clk_int)
begin
if rising_edge(sys_spi_clk_int) then
if (clk_sys_rstn = '0') then
fmc_debug <= '0';
else
fmc_debug <= sys_spi_dout_int and
((not sys_spi_cs_adc0_n_int) or
(not sys_spi_cs_adc1_n_int) or
(not sys_spi_cs_adc2_n_int) or
(not sys_spi_cs_adc3_n_int));
end if;
end if;
end process;
--p_debug : process(sys_spi_clk_int)
--begin
-- if rising_edge(sys_spi_clk_int) then
-- if (clk_sys_rstn = '0') then
-- fmc_debug <= '0';
-- else
-- fmc_debug <= sys_spi_dout_int and
-- ((not sys_spi_cs_adc0_n_int) or
-- (not sys_spi_cs_adc1_n_int) or
-- (not sys_spi_cs_adc2_n_int) or
-- (not sys_spi_cs_adc3_n_int));
-- end if;
-- end if;
--end process;
-- The board peripherals components is slave 8
cmp_xwb_dbe_periph : xwb_dbe_periph
......@@ -1087,8 +1087,6 @@ begin
port map (
CONTROL => CONTROL0,
--CLK => clk_sys,
-- TEST. We need to have all adc chain sync to a single clock
-- domain
CLK => fmc516_fs_clk(c_adc_ref_clk),
--CLK => fmc516_fs_clk(1),
TRIG0 => TRIG_ILA0_0,
......
scripts/loader/_impactbatch.log 0 → 100644
View file @ 48a98478
iMPACT Version: Jan 6 2012 20:13:43
iMPACT log file Started on Mon Jun 17 18:02:14 2013
Preference Table
Name Setting
StartupClock Auto_Correction
AutoSignature False
KeepSVF False
ConcurrentMode False
UseHighz False
ConfigOnFailure Stop
UserLevel Novice
MessageLevel Detailed
svfUseTime false
SpiByteSwap Auto_Correction
AutoInfer false
SvfPlayDisplayComments false
AutoDetecting cable. Please wait.
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/xusbdfwu.hex = 1030.
File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1030.
Using libusb.
Kernel release = 3.8.0-25-generic.
Max current requested during enumeration is 74 mA.
Type = 0x0004.
Cable Type = 3, Revision = 0.
Setting cable speed to 6 MHz.
Cable connection established.
Firmware version = 1303.
File version of /opt/Xilinx/13.4/ISE_DS/ISE/data/xusb_xlp.hex = 1303.
Firmware hex file version = 1303.
PLD file version = 0012h.
PLD version = 0012h.
Type = 0x0004.
ESN option: 000013C8040F01.
Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6vlx240t, Version : 6
INFO:iMPACT:1777 -
Reading /opt/Xilinx/13.4/ISE_DS/ISE/virtex6/data/xc6vlx240t.bsd...
INFO:iMPACT:501 - '1': Added Device xc6vlx240t successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
'1': : Manufacturer's ID = Xilinx xccace, Version : 0
INFO:iMPACT:1777 -
Reading /opt/Xilinx/13.4/ISE_DS/ISE/acecf/data/xccace.bsd...
INFO:iMPACT:501 - '1': Added Device xccace successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
done.
Elapsed time = 0 sec.
Elapsed time = 0 sec.
'2': Loading file '../../hdl/syn/dbe_bpm_fmc516/dbe_bpm_fmc516.bit' ...
done.
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
----------------------------------------------------------------------
INFO:iMPACT:501 - '2': Added Device xc6vlx240t successfully.
----------------------------------------------------------------------
----------------------------------------------------------------------
Maximum TCK operating frequency for this device chain: 16700000.
Validating chain...
Boundary-scan chain validated successfully.
2: Device Temperature: Current Reading: 32.66 C, Min. Reading: 29.21 C, Max.Reading: 33.15 C
2: VCCINT Supply: Current Reading: 1.011 V, Min. Reading: 1.011 V, Max.Reading: 1.014 V
2: VCCAUX Supply: Current Reading: 2.511 V, Min. Reading: 2.508 V, Max.Reading: 2.520 V
'2': Programming device...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 1011 1110 0000 1011 1000 0000
INFO:iMPACT:579 - '2': Completed downloading bit file to device.
INFO:iMPACT:188 - '2': Programming completed successfully.
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '2': Checking done pin....done.
'2': Programmed successfully.
Elapsed time = 20 sec.
----------------------------------------------------------------------
----------------------------------------------------------------------
scripts/loader/program_fpga 0 → 100755
View file @ 48a98478
#!/bin/bash
TOP_DIR=../..
DEFAULT_SYN_PATH=${TOP_DIR}/hdl/syn
EXPECTED_ARGS=1
# Test for parameter presence
: ${1?"Usage: $0 <bistream_name>"}
BITSTREAM=$1
#Search for bistream
BITSTREAM_LOC=$(find ${DEFAULT_SYN_PATH} -regextype posix-extended -iregex ".*${BITSTREAM}.*bit" -print)
BITSTREAM_NUM=$(echo -e "${BITSTREAM_LOC}" | wc -l)
if [ "${BITSTREAM_NUM}" -gt 1 ]; then
echo -e "There are "${BITSTREAM_NUM}" bitstreams that matches the description:"
echo "${BITSTREAM_LOC}"
echo "You must specify a more verbose name"
exit 1
fi
# Write the commands to a temporary file
cat > .impact_batch << EOF
setMode -bscan
setCable -port auto
identify
assignFile -p 2 -file ${BITSTREAM_LOC}
program -p 2
closeCable
quit
EOF
impact -batch .impact_batch
rm .impact_batch
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