testbench/*/wb_acq_core_test/**: add script to remove generated libs

4d16d468 · Lucas Russo · ab8f5f5e · 4d16d468
Commit 4d16d468 authored Dec 18, 2015 by Lucas Russo
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questa_remove_libs.sh ...ore_test/verilog/artix7/full_tb_mux/questa_remove_libs.sh +8 -0

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--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/questa_remove_libs.sh
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/questa_remove_libs.sh
+rm -rf xil_defaultlib
+rm -rf fifo_generator_v12_0
+rm -rf axi_interconnect_v1_7
+rm -rf lib_pkg_v1_0
+rm -rf lib_fifo_v1_0
+rm -rf lib_srl_fifo_v1_0
+rm -rf lib_cdc_v1_0
+rm -rf axi_datamover_v5_1