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Commit 4eaaadf0 authored by Lucas Russo's avatar Lucas Russo
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hdl/modules/*/wb_rs232/*: add rs232 wishbone master

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hdl/modules/dbe_wishbone/Manifest.py
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......@@ -6,5 +6,6 @@ modules = { "local" : [
"wb_fmc516",
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph"
"wb_dbe_periph",
"wb_rs232_syscon"
] };
hdl/modules/dbe_wishbone/wb_rs232_syscon/Manifest.py 0 → 100644
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files = [ "auto_baud.v",
"rs232_syscon.v",
"rs232_syscon_top.v",
"wb_rs232_syscon.vhd",
"xwb_rs232_syscon.vhd",
"serial.v" ]
hdl/modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v 0 → 100644
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hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v 0 → 100644
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hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v 0 → 100644
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module rs232_syscon_top_1_0 (
input clk_i,
input reset_i,
input ack_i,
input err_i,
input rs232_rxd_i,
input [31:0]data_in,
output [31:0]data_out,
output rst_o,
output stb_o,
output cyc_o,
output [31:0]adr_o,
output we_o,
output rs232_txd_o,
output [3:0]sel_o
);
wire syscon_master;
assign sel_o[3] = stb_o;
assign sel_o[2] = stb_o;
assign sel_o[1] = stb_o;
assign sel_o[0] = stb_o;
// Auto-baud
// dat_io -> data_in i data_out
// Magistrala
// Adres: 16 bit
// Dane: 32 bit
rs232_syscon i_rs232_syscon (
.clk_i(clk_i),
.reset_i(reset_i),
.ack_i(ack_i),
.err_i(err_i),
.master_bg_i(syscon_master),
.master_adr_i(),
.master_stb_i(),
.master_we_i(),
.rs232_rxd_i(rs232_rxd_i),
//.rs232_rxd_i(),
.data_in(data_in),
.data_out(data_out),
//.dat_io(data),
.rst_o(rst_o),
.master_br_o(syscon_master),
.stb_o(stb_o),
.cyc_o(cyc_o),
.adr_o(adr_o),
.we_o(we_o),
//.rs232_txd_o()
.rs232_txd_o(rs232_txd_o)
);
endmodule
hdl/modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.xml 0 → 100644
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<?xml version="1.0" encoding="utf-8"?>
<wb_driver nazwa="rs232_syscon_top" wersja="1.0">
<interface>
<line nazwa="rs232_rxd_i" typ="input" />
<line nazwa="rs232_txd_o" typ="output" />
</interface>
<wb_interface>
<line nazwa="clk_i" wb_name="wb_clk" />
<line nazwa="reset_i" wb_name="reset" />
<line nazwa="rst_o" wb_name="wb_rst" />
<line nazwa="cyc_o" wb_name="wb_cyc" />
<line nazwa="adr_o" wb_name="wb_adr" />
<line nazwa="data_in" wb_name="wb_data_out" />
<line nazwa="we_o" wb_name="wb_we" />
<line nazwa="stb_o" wb_name="wb_stb" />
<line nazwa="data_out" wb_name="wb_data_in" />
<line nazwa="ack_i" wb_name="wb_ack" />
<line nazwa="err_i" wb_name="wb_err" />
<line nazwa="sel_o" wb_name="wb_sel" />
</wb_interface>
</wb_driver>
hdl/modules/dbe_wishbone/wb_rs232_syscon/serial.v 0 → 100644
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hdl/modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd 0 → 100644
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------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-26-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone Wrapper for RS232 Master
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-26-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
entity wb_rs232_syscon is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
m_wb_adr_o : out std_logic_vector(31 downto 0);
m_wb_sel_o : out std_logic_vector(3 downto 0);
m_wb_we_o : out std_logic;
m_wb_dat_o : out std_logic_vector(31 downto 0);
m_wb_dat_i : in std_logic_vector(31 downto 0);
m_wb_cyc_o : out std_logic;
m_wb_stb_o : out std_logic;
m_wb_ack_i : in std_logic;
m_wb_err_i : in std_logic;
m_wb_stall_i : in std_logic;
m_wb_rty_i : in std_logic
);
end wb_rs232_syscon;
architecture rtl of wb_rs232_syscon is
signal rst : std_logic;
signal rst_out : std_logic;
signal m_wb_adr_out : std_logic_vector(31 downto 0);
signal m_wb_sel_out : std_logic_vector(3 downto 0);
signal m_wb_we_out : std_logic;
signal m_wb_dat_out : std_logic_vector(31 downto 0);
signal m_wb_dat_in : std_logic_vector(31 downto 0);
signal m_wb_cyc_out : std_logic;
signal m_wb_stb_out : std_logic;
signal m_wb_ack_in : std_logic;
signal m_wb_err_in : std_logic;
signal m_wb_stall_in : std_logic;
signal m_wb_rty_in : std_logic;
component rs232_syscon_top_1_0
port (
clk_i : in std_logic;
reset_i : in std_logic;
ack_i : in std_logic;
err_i : in std_logic;
rs232_rxd_i : in std_logic;
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
rst_o : out std_logic;
stb_o : out std_logic;
cyc_o : out std_logic;
adr_o : out std_logic_vector(31 downto 0);
we_o : out std_logic;
rs232_txd_o : out std_logic;
sel_o : out std_logic_vector(3 downto 0)
);
end component;
begin
rst <= not wb_rstn_i;
-- ETHMAC master interface is byte addressed, classic wishbone
cmp_ma_iface_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => false,
g_master_mode => g_ma_interface_mode,
g_master_granularity => g_ma_address_granularity,
g_slave_use_struct => false,
g_slave_mode => CLASSIC,
g_slave_granularity => BYTE
)
port map (
clk_sys_i => wb_clk_i,
rst_n_i => wb_rstn_i,
sl_adr_i => m_wb_adr_out,
sl_dat_i => m_wb_dat_out,
sl_sel_i => m_wb_sel_out,
sl_cyc_i => m_wb_cyc_out,
sl_stb_i => m_wb_stb_out,
sl_we_i => m_wb_we_out,
sl_dat_o => m_wb_dat_in,
sl_ack_o => m_wb_ack_in,
sl_stall_o => open,
sl_int_o => open,
sl_rty_o => open,
sl_err_o => m_wb_err_in,
ma_adr_o => m_wb_adr_o,
ma_dat_o => m_wb_dat_o,
ma_sel_o => m_wb_sel_o,
ma_cyc_o => m_wb_cyc_o,
ma_stb_o => m_wb_stb_o,
ma_we_o => m_wb_we_o,
ma_dat_i => m_wb_dat_i,
ma_ack_i => m_wb_ack_i,
ma_stall_i => m_wb_stall_i,
ma_rty_i => m_wb_rty_i,
ma_err_i => m_wb_err_i
);
cmp_rs232_syscon_top_1_0 : rs232_syscon_top_1_0
port map (
clk_i => wb_clk_i,
reset_i => rst,
ack_i => m_wb_ack_in,
err_i => m_wb_err_in,
rs232_rxd_i => rs232_rxd_i,
data_in => m_wb_dat_in,
data_out => m_wb_dat_out,
rst_o => rst_out,
stb_o => m_wb_stb_out,
cyc_o => m_wb_cyc_out,
adr_o => m_wb_adr_out,
we_o => m_wb_we_out,
rs232_txd_o => rs232_txd_o,
sel_o => m_wb_sel_out
);
rstn_o <= not rst_out;
end rtl;
hdl/modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd 0 → 100644
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------------------------------------------------------------------------------
-- Title : Wishbone Ethernet MAC Wrapper
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-26-08
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone Wrapper for RS232 Master
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-26-08 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
use work.dbe_wishbone_pkg.all;
entity xwb_rs232_syscon is
generic (
g_ma_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_ma_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- WISHBONE common
wb_clk_i : in std_logic;
wb_rstn_i : in std_logic;
-- External ports
rs232_rxd_i : in std_logic;
rs232_txd_o : out std_logic;
-- Reset to FPGA logic
rstn_o : out std_logic;
-- WISHBONE master
wb_master_i : in t_wishbone_master_in;
wb_master_o : out t_wishbone_master_out
);
end xwb_rs232_syscon;
architecture rtl of xwb_rs232_syscon is
begin
cmp_wb_rs232_syscon : wb_rs232_syscon
generic map (
g_ma_interface_mode => g_ma_interface_mode,
g_ma_address_granularity => g_ma_address_granularity
)
port map(
-- WISHBONE common
wb_clk_i => wb_clk_i,
wb_rstn_i => wb_rstn_i,
-- External ports
rs232_rxd_i => rs232_rxd_i,
rs232_txd_o => rs232_txd_o,
-- Reset to FPGA logic
rstn_o => rstn_o,
-- WISHBONE master
m_wb_adr_o => wb_master_o.adr,
m_wb_sel_o => wb_master_o.sel,
m_wb_we_o => wb_master_o.we,
m_wb_dat_o => wb_master_o.dat,
m_wb_dat_i => wb_master_i.dat,
m_wb_cyc_o => wb_master_o.cyc,
m_wb_stb_o => wb_master_o.stb,
m_wb_ack_i => wb_master_i.ack,
m_wb_err_i => wb_master_i.err,
m_wb_stall_i => wb_master_i.stall,
m_wb_rty_i => wb_master_i.rty
);
end rtl;
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