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Commit 5221b0d9 authored by Lucas Russo's avatar Lucas Russo
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syn/dbe_bpm_simple/*: updated dbe_simple_top synthesis files

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hdl/syn/dbe_bpm_simple/dbe_bpm_simple.gise
View file @ 5221b0d9
......@@ -72,41 +72,39 @@
</files>
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.lso"/>
......@@ -120,24 +118,22 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1349988422" xil_pn:in_ck="1309770857089352171" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6566612260269040355" xil_pn:start_ts="1349988422">
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1349988448" xil_pn:in_ck="4181690111764201426" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8990626865624946785" xil_pn:start_ts="1349988422">
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<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bld"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ngd"/>
<outfile xil_pn:name="dbe_bpm_simple_top_ngdbuild.xrpt"/>
</transform>
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<transform xil_pn:end_ts="1350157031" xil_pn:in_ck="-956280685729320234" xil_pn:name="TRANEXT_map_virtex6" xil_pn:prop_ck="5939692501008836605" xil_pn:start_ts="1350156884">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.pcf"/>
<outfile xil_pn:name="dbe_bpm_simple_top_map.map"/>
......@@ -148,11 +144,10 @@
<outfile xil_pn:name="dbe_bpm_simple_top_summary.xml"/>
<outfile xil_pn:name="dbe_bpm_simple_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1349988722" xil_pn:in_ck="-4414935198573544209" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="6734387949470617483" xil_pn:start_ts="1349988599">
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<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.ncd"/>
<outfile xil_pn:name="dbe_bpm_simple_top.pad"/>
......@@ -164,11 +159,10 @@
<outfile xil_pn:name="dbe_bpm_simple_top_pad.txt"/>
<outfile xil_pn:name="dbe_bpm_simple_top_par.xrpt"/>
</transform>
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<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bgn"/>
<outfile xil_pn:name="dbe_bpm_simple_top.bit"/>
......@@ -177,14 +171,13 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
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<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputRemoved"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="dbe_bpm_simple_top.twr"/>
<outfile xil_pn:name="dbe_bpm_simple_top.twx"/>
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</transforms>
......
hdl/syn/dbe_bpm_simple/dbe_bpm_simple.xise
View file @ 5221b0d9
......@@ -101,6 +101,7 @@
<property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
......@@ -158,6 +159,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -217,6 +221,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -306,6 +311,7 @@
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
......
hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bgn
View file @ 5221b0d9
......@@ -6,7 +6,7 @@ Loading device for application Rf_Device from file '6vlx240t.nph' in environment
ff1156, speed -1
Opened constraints file dbe_bpm_simple_top.pcf.
Thu Oct 11 17:52:18 2012
Sat Oct 13 16:39:57 2012
/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:2 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g Disable_JTAG:No -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ConfigFallback:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g USR_ACCESS:None -g next_config_addr:None -g JTAG_SysMon:Enable -g DCIUpdateMode:Quiet -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No dbe_bpm_simple_top.ncd
......@@ -156,14 +156,14 @@ WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by
a combinatorial pin. This is not good design practice. Use the CE pin to
control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring5_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring4_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring2_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring5_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring1_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
......
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