Skip to content

B
Beam Positoning Monitor - Gateware
Commit 525f5ca5 authored by Adrian Byszuk's avatar Adrian Byszuk
Browse files
Options

Update DDR core & add calibration patch (AR#53420)

parent 0fcc2290
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 535 additions and 453 deletions
hdl/ip_cores/pcie/7k325ffg900/Manifest.py
View file @ 525f5ca5
......@@ -14,5 +14,5 @@ else:
"prime_FIFO_plain.vhd",
"sfifo_15x128.vhd"]
modules = {"local" : ["pcie_core/source"],
["ddr_core/user_design"]}
modules = {"local" : ["pcie_core/source",
"ddr_core/user_design"]}
hdl/ip_cores/pcie/7k325ffg900/coregen.cgc
View file @ 525f5ca5
This diff is collapsed.
hdl/ip_cores/pcie/7k325ffg900/ddr_core.xco
View file @ 525f5ca5
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Jan 17 19:57:44 2013
# Date: Tue Feb 19 17:29:02 2013
#
##############################################################
#
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core.xise
View file @ 525f5ca5
......@@ -681,8 +681,8 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-17T20:57:46" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C640F3022B2148EAF56295693B0B039A" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-19T18:29:04" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="434C2AF05675FD3B82C582C8653F7186" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core/mig.prj
View file @ 525f5ca5
......@@ -11,7 +11,7 @@
<TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
<Version>1.8</Version>
<SystemClock>Differential</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<ReferenceClock>Use System Clock</ReferenceClock>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>0</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ddr_core.vhd
View file @ 525f5ca5
......@@ -113,7 +113,7 @@ entity ddr_core is
PAYLOAD_WIDTH : integer := 64;
ECC_WIDTH : integer := 8;
MC_ERR_ADDR_WIDTH : integer := 31;
nBANK_MACHS : integer := 4;
RANKS : integer := 1;
-- # of Ranks.
......@@ -207,7 +207,7 @@ entity ddr_core is
-- = "OFF" - Components, SODIMMs, UDIMMs.
CA_MIRROR : string := "OFF";
-- C/A mirror opt for DDR3 dual rank
--***************************************************************************
-- The following parameters are multiplier and divisor factors for PLLE2.
-- Based on the selected design frequency these parameters vary.
......@@ -399,10 +399,10 @@ entity ddr_core is
SYSCLK_TYPE : string := "DIFFERENTIAL";
-- System clock type DIFFERENTIAL, SINGLE_ENDED,
-- NO_BUFFER
REFCLK_TYPE : string := "NO_BUFFER";
REFCLK_TYPE : string := "USE_SYSTEM_CLOCK";
-- Reference clock type DIFFERENTIAL, SINGLE_ENDED
-- NO_BUFFER, USE_SYSTEM_CLOCK
CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
DRAM_TYPE : string := "DDR3";
......@@ -442,7 +442,7 @@ entity ddr_core is
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL";
-- # = "INTERNAL", "EXTERNAL"
RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
......@@ -473,8 +473,7 @@ entity ddr_core is
-- Differential system clocks
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
-- Single-ended iodelayctrl clk (reference clock)
clk_ref_i : in std_logic;
-- user interface signals
app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
......@@ -496,12 +495,12 @@ entity ddr_core is
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System reset
sys_rst : in std_logic
......@@ -532,7 +531,7 @@ architecture arch_ddr_core of ddr_core is
return "OFF";
end if;
end function;
constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
......@@ -544,8 +543,8 @@ architecture arch_ddr_core of ddr_core is
-- Enable or disable the temp monitor module
constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
......@@ -612,7 +611,7 @@ architecture arch_ddr_core of ddr_core is
ref_dll_lock : in std_logic
);
end component mig_7series_v1_8_infrastructure;
component mig_7series_v1_8_tempmon is
generic (
TCQ : integer;
......@@ -882,10 +881,10 @@ architecture arch_ddr_core of ddr_core is
dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0)
);
end component mig_7series_v1_8_memc_ui_top_std;
-- Signal declarations
signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
signal clk : std_logic;
signal clk_ref : std_logic;
......@@ -899,16 +898,15 @@ architecture arch_ddr_core of ddr_core is
signal rst_phaser_ref : std_logic;
signal rst : std_logic;
signal app_ecc_multiple_err : std_logic_vector(2*nCK_PER_CLK-1 downto 0);
signal ddr3_parity : std_logic;
signal init_calib_complete_i : std_logic;
signal sys_clk_i : std_logic;
signal mmcm_clk : std_logic;
signal clk_ref_p : std_logic;
signal clk_ref_n : std_logic;
signal clk_ref_i : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
signal device_temp_i : std_logic_vector(11 downto 0);
......@@ -985,7 +983,9 @@ architecture arch_ddr_core of ddr_core is
signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
signal all_zeros : std_logic_vector(2*nCK_PER_CLK-1 downto 0) := (others => '0');
signal clk_ref_p : std_logic := '0';
signal clk_ref_n : std_logic := '0';
begin
......@@ -997,12 +997,11 @@ begin
ui_clk <= clk;
ui_clk_sync_rst <= rst;
sys_clk_i <= '0';
clk_ref_p <= '0';
clk_ref_n <= '0';
clk_ref_i <= '0';
init_calib_complete <= init_calib_complete_i;
clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
......@@ -1071,7 +1070,7 @@ begin
temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
device_temp <= (others => '0');
end generate;
u_ddr3_infrastructure : mig_7series_v1_8_infrastructure
generic map
......@@ -1363,7 +1362,7 @@ begin
init_calib_complete => init_calib_complete_i
);
......@@ -1387,6 +1386,6 @@ begin
dbg_po_f_stg23_sel <= '0';
dbg_sel_po_incdec <= '0';
end architecture arch_ddr_core;
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ip_top/mig_7series_v1_8_memc_ui_top_std.v
View file @ 525f5ca5
......@@ -68,7 +68,7 @@
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v1_8_ddr3_7Series, Coregen 14.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_8,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8jtf12864hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=NO_BUFFER}" *)
(* X_CORE_INFO = "mig_7series_v1_8_ddr3_7Series, Coregen 14.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_8,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8jtf12864hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v1_8_memc_ui_top_std #
(
parameter TCQ = 100,
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_mc_phy_wrapper.v
View file @ 525f5ca5
......@@ -474,15 +474,18 @@ module mig_7series_v1_8_ddr_mc_phy_wrapper #
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK <= 938) ? 23 :
(tCK <= 1072) ? 24 :
(tCK <= 1250) ? 25 :
(tCK <= 1500) ? 26 : 27;
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
(tCK > 2500) ? 8 : 30 :
(tCK > 2500) ? 8 : PHY_0_A_PO_OCLK_DELAY_HW :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
......
hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/phy/mig_7series_v1_8_ddr_phy_wrlvl.v
View file @ 525f5ca5
......@@ -214,9 +214,9 @@ module mig_7series_v1_8_ddr_phy_wrlvl #
reg [2:0] corse_dec[0:DQS_WIDTH-1];
reg [2:0] corse_inc[0:DQS_WIDTH-1];
reg dq_cnt_inc;
reg [2:0] stable_cnt;
reg [3:0] stable_cnt;
reg flag_ck_negedge;
reg past_negedge;
//reg past_negedge;
reg flag_init;
reg [2:0] corse_cnt[0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;
......@@ -275,15 +275,15 @@ module mig_7series_v1_8_ddr_phy_wrlvl #
assign dbg_phy_wrlvl[32+:4] = dqs_count_r;
assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;
assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;
assign dbg_phy_wrlvl[54+:3] = stable_cnt;
assign dbg_phy_wrlvl[57] = past_negedge;
assign dbg_phy_wrlvl[58] = flag_ck_negedge;
assign dbg_phy_wrlvl[54+:4] = stable_cnt;
assign dbg_phy_wrlvl[58] = 'd0;
assign dbg_phy_wrlvl[59] = flag_ck_negedge;
assign dbg_phy_wrlvl [59] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [60+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [66+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [75+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [129+:27] = wl_po_coarse_cnt;
assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;
......@@ -663,8 +663,9 @@ endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || (wl_state_r == WL_INIT_FINE_INC_WAIT) ||
(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||
//(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
......@@ -679,39 +680,40 @@ endgenerate
(wl_state_r == WL_FINE_DEC) |
(rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |
(wl_state_r1 == WL_INIT_FINE_DEC))
stable_cnt <= #TCQ 3'd0;
stable_cnt <= #TCQ 'd0;
else if ((wl_tap_count_r > 6'd0) &
(((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 3'd7))
& (stable_cnt < 'd14))
stable_cnt <= #TCQ stable_cnt + 1;
end
end
// Signal to ensure that flag_ck_negedge does not incorrectly assert
// when DQS is very close to CK rising edge
always @(posedge clk) begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
past_negedge <= #TCQ 1'b0;
else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
(stable_cnt == 3'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
(wl_state_r == WL_CORSE_INC_WAIT2)))
past_negedge <= #TCQ 1'b1;
end
//always @(posedge clk) begin
// if (rst | (wl_state_r == WL_DQS_CNT) |
// (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
// past_negedge <= #TCQ 1'b0;
// else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
// (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
// (wl_state_r == WL_CORSE_INC_WAIT2)))
// past_negedge <= #TCQ 1'b1;
//end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) | past_negedge |
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r |
(wl_state_r1 == WL_INIT_FINE_DEC))
flag_ck_negedge <= #TCQ 1'd0;
else if (rd_data_previous_r[dqs_count_r] && ((stable_cnt > 3'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1)))
else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |
(wl_state_r == WL_CORSE_INC))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 3'd7))
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
......@@ -737,7 +739,7 @@ endgenerate
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 3'd7))
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);
......@@ -856,8 +858,8 @@ endgenerate
end
// Initially Phaser_Out fine delay taps incremented
// until stable_cnt=7. A stable_cnt of 7 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 7 fine
// until stable_cnt=14. A stable_cnt of 14 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 14 fine
// tap increments. This is done to inhibit false 0->1
// edge detection when DQS is initially aligned to the
// negedge of CK
......@@ -881,7 +883,7 @@ endgenerate
// undetected.
WL_INIT_FINE_INC_WAIT: begin
if (wl_sm_start) begin
if (stable_cnt < 'd7)
if (stable_cnt < 'd14)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
else if (~rd_data_previous_r[dqs_count_r]) begin
wl_state_r <= #TCQ WL_WAIT;
......@@ -1103,9 +1105,9 @@ endgenerate
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// For initial writes check only upto 41 taps. Reserving the
// For initial writes check only upto 56 taps. Reserving the
// remaining taps for OCLK calibration.
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd41)) begin
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin
if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment